Liquid Crystal Display Transistor Layout for Lateral Visibility
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Solution Overview
Problem
Liquid crystal displays with a vertically aligned mode have lower lateral visibility compared to front visibility, and existing solutions to improve this, such as dividing a pixel into sub-pixels and applying different voltages, are limited in adjusting voltage ratios and increasing transistor arrangement and size flexibility.
Innovation Solution
A liquid crystal display design that includes multiple transistors and capacitors, allowing for easy adjustment of voltage ratios between sub-pixels, reduction of light leakage current, and increased freedom in transistor arrangement and size control, thereby improving lateral visibility.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Illumination intensity
If a pixel is divided into two sub-pixels with different voltages applied to improve lateral visibility, then lateral visibility is improved, but the adjustment of voltage ratio becomes complex and transistor arrangement flexibility is reduced
Solution Approach 1:
The pixel is divided into two sub-pixels (first sub-pixel and second sub-pixel) with separate liquid crystal capacitors (first liquid crystal capacitor and second liquid crystal capacitor). Each sub-pixel has its own transistor (first transistor and second transistor) that can be independently controlled. This segmentation allows different voltages to be applied to each sub-pixel, improving lateral visibility while maintaining independent control for simple voltage ratio adjustment.
2Ease of manufacture
If traditional transistor arrangements are used in vertically aligned mode displays, then manufacturing is simplified, but light leakage current increases and design flexibility is limited
Solution Approach 1:
The gate electrode is designed with an asymmetric structure including a gate line and a gate electrode extending from the gate line. The semiconductor is positioned to overlap with the gate electrode, creating an asymmetric layout that optimizes the electric field distribution. This asymmetric design reduces light leakage current while maintaining ease of manufacture through standard fabrication processes.
3Manufacturing precision
If fixed transistor sizes and arrangements are used, then manufacturing precision is maintained, but design freedom for optimizing display performance is reduced
Solution Approach 1:
The transistor design allows for dynamic adjustment of the semiconductor length and width dimensions. The gate electrode can be extended or shortened, and the semiconductor region can be adjusted in size while maintaining the overlapping relationship with the gate electrode. This dynamic design capability enables optimization of transistor performance for different display requirements while maintaining manufacturing precision through controlled fabrication parameters.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The design enhances lateral visibility, reduces light leakage, and increases design flexibility for transistor arrangement and size, particularly beneficial for high-resolution displays.
Implementation Method 1
When the voltage is applied to the field-generating electrodes, an electric field is generated in the liquid crystal layer, and the liquid crystal molecules are rearranged, and accordingly, desired images may be displayed by controlling an amount of transmitted light.
Implementation Method 2
The liquid crystal display may include at least one polarizer for adjusting the amount of transmitted light.
Data Source
AI summary
A liquid crystal display includes a gate line; a data line crossing the gate line; a first voltage line spaced apart from the gate line; a second voltage line, a first transistor including a first gate electrode connected to the gate line, a first source electrode connected to the data line, and a first drain electrode; a second transistor including a second gate electrode connected to the gate line, a second source electrode connected to the data line, and a second drain electrode; a third transistor including a third gate electrode connected to the first voltage line, a third source electrode connected to the second drain electrode, and a third drain electrode connected to the second voltage line; a first liquid crystal capacitor connected to the first drain electrode of the first transistor; and a second liquid crystal capacitor connected to the second drain electrode of the second transistor.