LCD Transistor Segmented Channel Resistance Ratio

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Solution Overview

Problem

In liquid crystal display (LCD) devices, accurately setting up the resistance ratio between transistors is challenging due to differences in transistor channel shapes, leading to distorted voltage ratios and degraded image quality.

Innovation Solution

The design includes a first, second, and third transistor with specific configurations such as varying channel regions and electrode shapes, allowing for a controlled resistance ratio by adjusting the number and arrangement of channel regions and electrode protrusions, ensuring accurate voltage distribution between sub-pixel electrodes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If one transistor has a channel region with different shape to reduce transistor size, then transistor size is reduced, but resistance ratio prediction becomes difficult and design complexity increases

Engineering Contradiction:
Improvetransistor sizeVSAvoiddesign complexity
Core Design Contradiction:
Volume of moving objectVSDevice complexity

Solution Approach 1:

The channel region of one transistor is divided into multiple segmented channel regions (e.g., first channel region and second channel region). This segmentation allows the transistor to achieve compact size while maintaining predictable resistance characteristics, as each segment can be designed with standard dimensions and the total resistance is the sum of individual segment resistances.

Inventive Principle:
Principle #1Segmentation

2Adaptability or versatility

If transistors have different internal resistance levels for sub-pixel voltage division, then voltage can be divided between sub-pixels, but accurate resistance ratio setup becomes challenging

Engineering Contradiction:
Improvevoltage division capabilityVSAvoidresistance ratio accuracy
Core Design Contradiction:
Adaptability or versatilityVSManufacturing precision

Solution Approach 1:

Different regions of the transistor channel are designed with specific local properties. The segmented channel regions have controlled dimensions and configurations that locally determine resistance characteristics, allowing precise control of the overall resistance ratio while maintaining manufacturing feasibility.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If resistance ratio between transistors is not accurate, then manufacturing is simpler, but voltage ratio becomes distorted and image quality degrades

Engineering Contradiction:
Improvetransistor manufacturingVSAvoidimage quality
Core Design Contradiction:
Ease of manufactureVSReliability

Solution Approach 1:

The transistor design incorporates predetermined channel region configurations and dimensions that are established during the design phase. This preliminary structuring ensures that the resistance ratio is inherently controlled by the physical geometry rather than requiring post-manufacturing adjustment, thereby guaranteeing accurate voltage division and image quality.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS9864239B2Liquid crystal display device
Publication Date: 2018.01.09 LONESTAR CRYSTAL DISPLAY LLC
  • US9864239B2 patent drawing
  • US9864239B2 patent drawing
  • US9864239B2 patent drawing

AI summary

A liquid crystal display (“LCD”) device capable of easily setting up an accurate resistance ratio between thin film transistors, the LCD device includes a first substrate including a gate line and a data line, a second substrate opposing the first substrate, a liquid crystal layer between the first substrate and the second substrate, a first sub-pixel electrode in a first sub-pixel region of the first substrate, a second sub-pixel electrode in a second sub-pixel region of the first substrate, a first transistor connected to the gate line, the data line, and the first sub-pixel electrode, a second transistor connected to the gate line, the first transistor, and the second sub-pixel electrode, and a third transistor connected to the gate line, the second sub-pixel electrode, and a storage line, wherein one of the first, second, and third transistors includes a plurality of divided channel regions.