Trench Gate Insulating Layer for LCD Data Line Isolation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Liquid crystal display devices, particularly in TN, PVA, and ECB modes, face issues with narrowing viewing angles due to refractive anisotropy of liquid crystal molecules when a voltage is applied, and there is a risk of shorting between the data line and pixel electrode during the manufacturing process in PLS mode.
Innovation Solution
The liquid crystal display device incorporates a gate insulating layer with a trench parallel to the data line, where the data line is disposed inside the trench, and a common electrode insulated from the pixel electrode, along with a semiconductor layer and electrodes on a base substrate, to prevent shorting and enhance viewing angles.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If the data line is disposed close to the pixel electrode to improve wiring density, then the device complexity is reduced, but the risk of shorting between the data line and pixel electrode increases
Solution Approach 1:
The gate insulating layer with a trench structure serves as an intermediary barrier between the data line and pixel electrode. The trench is formed in the gate insulating layer to receive and isolate the data line, preventing direct contact with the pixel electrode while maintaining close proximity for efficient wiring.
2Ease of manufacture
If liquid crystal molecules are vertically oriented to simplify the display mode, then the manufacturing process is easier, but the viewing angle becomes narrower
Solution Approach 1:
The patent applies different orientation characteristics to different regions of the liquid crystal layer. By controlling the anchoring conditions at the substrate interfaces and utilizing the trench structure, the liquid crystal molecules exhibit localized orientation variations that improve viewing angles while maintaining manufacturing simplicity.
Data Source
AI summary
A liquid crystal device including an array substrate facing an opposite substrate; and a liquid crystal layer between the array and opposite substrate, the array substrate including a gate electrode and gate line on a base substrate; a gate insulating layer covering the gate electrode and including a trench crossing the gate line; a semiconductor layer on the gate insulating layer and including a channel area overlapping the gate electrode, a source area at one side of the channel area, and a drain area at another side of the channel area; a pixel electrode on the gate insulating layer and spaced apart from the semiconductor layer; a source electrode connected to the source area; a drain electrode connected to the drain area and the pixel electrode; a data line connected to the source electrode and being inside the trench; and a common electrode insulated from the pixel electrode.