LCP Solder Mask Laminated to Interconnect Stack
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Solution Overview
Problem
The miniaturization of integrated circuits with closely arranged input and output pins creates a gap in interconnection technology, as printed wiring boards struggle to match the smaller solder pad spacing, leading to larger package sizes and limited system miniaturization.
Innovation Solution
A method involving a thin liquid crystal polymer (LCP) solder mask is used to form an interconnect layer stack on a rigid wafer substrate with patterned electrical conductor layers, dielectric layers, and solder pads, aligned with LCP apertures for precise solder placement and attachment of circuit components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If printed wiring boards are used to connect integrated circuits with closely arranged I/O pins, then the I/O pads can be connected, but the solder pad spacing on the PWB cannot match the finer pitch of the IC, resulting in larger package size
Solution Approach 1:
The patent transitions from traditional planar PWB interconnection to a three-dimensional wafer-level interconnect layer stack structure. Multiple conductor layers are stacked vertically with dielectric layers in between, enabling fine-pitch solder pads to be arranged in a compact 3D configuration that matches the IC footprint without increasing package size.
Solution Approach 2:
The interconnect layer stack embeds multiple conductor layers and dielectric layers within each other in a nested configuration. The solder pads are integrated within this stacked structure at the wafer level, allowing the interconnection system to be contained within the IC package footprint rather than extending outward.
2Adaptability or versatility
If extra routing layers or fan-out packaging are used to connect ICs to PWBs, then connectivity is achieved, but the package size increases beyond the IC size itself
Solution Approach 1:
The rigid wafer substrate with interconnect layer stack serves multiple functions simultaneously: it provides mechanical support, electrical interconnection through multiple conductor layers, solder mask protection, and component mounting surface. This multi-functional integration eliminates the need for separate PWB and fan-out structures, keeping the package size matched to the IC.
Solution Approach 2:
The patent merges the substrate, interconnect layers, solder mask, and component mounting functions into a single integrated wafer-level structure. The interconnect layer stack is formed directly on the rigid wafer substrate, and circuit components are attached directly to this integrated structure, combining multiple previously separate elements into one compact unit.
3Object-affected harmful factors
If a traditional solder mask is used, then solder pad protection is provided, but the device thickness increases
Solution Approach 1:
The patent uses a thin liquid crystal polymer (LCP) solder mask film to protect the solder pads. The LCP material provides effective solder mask functionality in a much thinner form factor compared to traditional solder masks, contributing to reduced overall device thickness while maintaining protection capabilities.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the creation of thinner electronic devices with finer pitch solder pad attachments, providing superior electrical isolation and protection, while allowing for the attachment of integrated circuits with narrow spacing without increasing the overall package size.
Implementation Method 1
Laminating the LCP solder mask and the interconnect layer stack together may be performed by applying heat and pressure to the LCP solder mask and the interconnect layer stack preferably in an autoclave
Implementation Method 2
Attaching the circuit component may be accomplished by heating the solder
Data Source
Figure 1
Figure 2A~2E
Figure 2F
AI summary
A method for making an electronic device includes forming an interconnect layer stack on a rigid wafer substrate having a plurality of patterned electrical conductor layers, a dielectric layer between adjacent patterned electrical conductor layers, and at least one solder pad on an uppermost patterned electrical conductor layer. An LCP solder mask having at least one aperture therein alignable with the at least one solder pad is formed. The LCP solder mask and interconnect layer stack are aligned and laminated together. Solder is positioned in the at least one aperture. At least one circuit component is attached to the at least one solder pad using the solder.