LCPLL Divider Calibration for Inductive Coupling Drift
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Solution Overview
Problem
In tightly packed System-on-Chips (SoCs), inductive coupling between clocking sources such as LCPLLs leads to frequency drift and timing errors due to close proximity, which existing solutions like increasing distance cannot practically address without increasing the integrated circuit area.
Innovation Solution
A calibration logic system that detects unwanted sideband frequencies and generates calibration codes using a Least Means Square scheme, applied to the clocking sources via their divider circuits to mitigate inductive coupling, allowing clocking sources to be in close proximity without performance degradation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LCPLLs are separated by a large distance to mitigate inductive coupling, then frequency stability is improved, but the integrated circuit area increases
Solution Approach 1:
The patent introduces a calibration logic system as an intermediary between the inductively coupled LCPLLs. This calibration logic detects unwanted sideband frequencies generated by inductive coupling and generates calibration codes that are applied to the LCPLLs via their divider circuits. The calibration logic acts as a mediator that enables close proximity placement of LCPLLs while maintaining frequency stability through active compensation rather than passive spatial separation.
Solution Approach 2:
The patent dynamically changes the operating parameters of the LCPLLs by applying calibration codes to their divider circuits. These calibration codes adjust the division ratios or frequency parameters of the LCPLLs to compensate for the frequency drift caused by inductive coupling. By changing parameters through calibration rather than changing physical distances, the system maintains frequency stability without increasing circuit area.
2Area of stationary object
If LCPLLs are placed in close proximity to reduce area, then integrated circuit area is reduced, but frequency drift and timing errors increase due to inductive coupling
Solution Approach 1:
The calibration logic implements a feedback mechanism by continuously monitoring the clock signals from closely spaced LCPLLs and detecting unwanted sideband frequencies. Based on this feedback information, the calibration logic generates appropriate calibration codes that are fed back to the LCPLLs to correct frequency drift. This closed-loop feedback system enables the LCPLLs to maintain frequency stability despite being placed in close proximity, resolving the contradiction between area reduction and frequency stability.
Solution Approach 2:
The calibration logic serves as an intermediary compensation system that allows LCPLLs to be placed close together. Instead of relying on physical distance to prevent inductive coupling, the calibration logic mediates the interaction between closely spaced LCPLLs by detecting their coupling effects and applying corrective calibration codes, thereby maintaining frequency stability while enabling compact layout.
3Adaptability or versatility
If multiple LCPLLs are used to provide different clocking frequencies, then clocking versatility is improved, but inductive coupling between clock sources increases
Solution Approach 1:
The calibration logic system provides a universal solution that can be applied to multiple different types of LCPLLs generating different clocking frequencies. The same calibration logic architecture and calibration methodology can accommodate various clock frequency requirements (e.g., 2.5 GHz for one I/O band, 2.38 GHz for another) while simultaneously managing the inductive coupling between all these diverse clock sources. This multi-functional calibration approach enables versatile clocking while controlling coupling noise.
Solution Approach 2:
The calibration logic acts as a universal intermediary that manages inductive coupling among multiple diverse clock sources. Rather than requiring different solutions for different frequency pairs, the calibration logic provides a unified approach that detects and compensates for coupling effects among any number of LCPLLs operating at different frequencies, thereby enabling clocking versatility while controlling harmful coupling noise.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This digital solution effectively reduces inductive coupling noise, enabling smaller SoC designs with minimal power consumption and improved integration by maintaining low jitter clock signals, thus enhancing system performance and reducing design time.
Implementation Method 1
the first and second LCPLLs are inductively coupled by respective inductors of the first and second LCPLLs
Data Source
AI summary
Described is an apparatus which comprises: a first clocking source having a first divider; a second clocking source having a second divider, wherein the first and second clocking sources are inductively coupled; and calibration logic to monitor clock signals associated with the first and second clocking sources and to generate at least one calibration code for adjusting at least one divider ratio of the first or second dividers according to the monitored clock signals.