Charge Sharing LCV Write Assist for SRAM
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Solution Overview
Problem
Existing SRAM memory devices face challenges with high active power consumption and area occupancy due to constant current bias circuitry used in write assist operations, which negatively impact memory density and efficiency.
Innovation Solution
The implementation of a charge sharing lower-cell-voltage (LCV) circuit that dynamically adjusts the bit cell power supply voltage using a capacitor formed between a bit cell power supply wire and a charge sharing wire in different metal layers, allowing for reduced voltage during write operations without increasing active power consumption or area usage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If constant current bias circuitry is used for write assist operations, then write speed is improved, but active power consumption increases
Solution Approach 1:
The patent implements dynamic voltage adjustment during write operations by selectively connecting the bit cell power supply to either the main power supply voltage or a lowered voltage through control circuitry. This dynamic switching allows the system to provide enhanced write assist voltage only when needed during write operations, rather than maintaining constant lowered voltage, thereby reducing active power consumption while preserving write speed improvements.
Solution Approach 2:
The patent changes the voltage parameter dynamically by providing two different power supply voltage levels (normal voltage and lowered voltage) and selectively switching between them based on the operation type. During write operations, the lowered voltage is applied to assist the write process, while during read operations, the normal voltage is restored, optimizing both write speed and power consumption characteristics.
2Speed
If bias circuitry is added to dynamically adjust power to bit cells, then write operations become faster, but area occupancy increases
Solution Approach 1:
The patent implements multi-functionality by using the existing power supply network and control logic to perform both normal power supply and write assist functions. The same power supply infrastructure is used for both read and write operations, with intelligent switching based on operation type. This eliminates the need for separate dedicated bias circuitry, reducing area occupancy while maintaining write speed improvements.
Solution Approach 2:
The control circuitry utilizes existing control signals and logic within the memory device to automatically manage the voltage switching during write operations. The system self-regulates by detecting write operation conditions and automatically applying the appropriate voltage level without requiring external bias circuitry, thereby reducing area occupancy while achieving faster write operations.
3Ease of operation
If constant lowered voltage is applied during write cycles, then write ease is improved, but power consumption across time increases
Solution Approach 1:
The patent applies lowered voltage periodically and selectively only during write operations rather than continuously. The control circuitry enables the lowered voltage to be applied in specific time windows corresponding to write cycles, and restores normal voltage during read operations and idle periods. This periodic application maintains write ease while significantly reducing energy loss across time.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enables faster and more efficient write operations with lower power consumption and improved memory density by utilizing otherwise unused metal layers for the charge sharing circuit, thereby enhancing data writing capabilities while minimizing resource utilization.
Implementation Method 1
a capacitor formed between a bit cell power supply wire and a charge sharing wire in different metal layers
Data Source
AI summary
A charge sharing type lower-cell-voltage (LCV) write assist takes advantage of unused metal layers on top of a memory array to implement capacitance without incurring area costs. Only one-time fixed amount expenses of charge are needed for a given LCV level during the charge sharing phase of each write operation. Metal wires parallel to the bit cell power wires have good capacitance matching for charge sharing among all memory density configurations, thus benefitting memory compiler design.