LDD Transistor Blocking Layer Layout for Leakage Suppression
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Solution Overview
Problem
Existing semiconductor devices face challenges in preventing leakage current, particularly in high-voltage transistors with lightly doped drain structures, which are prone to leakage due to strong electric fields and hot carrier effects.
Innovation Solution
The semiconductor device incorporates a semiconductor substrate with a lightly doped drain structure that includes low-concentration and high-concentration impurity regions, separated by blocking layers forming a 'U' shape, which prevent direct overlap and minimize leakage current by increasing the separation distance between these regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If a lightly doped drain structure is used in high-voltage transistors, then the transistor can operate at high voltage, but leakage current increases due to strong electric fields and hot carrier effects
Solution Approach 1:
A blocking layer is introduced as an intermediary between the low-concentration and high-concentration impurity regions. This blocking layer acts as a mediator that prevents direct interaction between the two regions, thereby blocking leakage current while maintaining the high-voltage operation capability of the transistor
Solution Approach 2:
The drain region is segmented into distinct low-concentration and high-concentration impurity regions separated by a blocking layer. This segmentation creates a multi-zone structure that addresses different functional requirements: the low-concentration region handles high-voltage operation while the high-concentration region provides good ohmic contact, with the blocking layer preventing harmful interactions between them
2Object-generated harmful factors
If the separation distance between low-concentration and high-concentration impurity regions is increased, then leakage current is reduced, but the device area increases
Solution Approach 1:
The blocking layer is positioned in the vertical dimension (depth direction) rather than extending the separation distance in the lateral dimension. By stacking the low-concentration and high-concentration regions vertically with the blocking layer between them, the design achieves effective separation without increasing the horizontal device footprint
Solution Approach 2:
The impurity regions are arranged in a nested vertical configuration where the low-concentration region, blocking layer, and high-concentration region are stacked one on top of another. This nested structure allows compact integration while maintaining the necessary separation to block leakage current
Data Source
AI summary
A semiconductor device may be provided and include: a semiconductor substrate including a semiconductor substrate; an active region on the semiconductor substrate; a device isolation region on a side surface of the active region; a first source/drain region and a second source/drain region spaced apart from each other within the active region; a channel region between the first source/drain region and the second source/drain region, within the active region; a gate electrode extending across the active region in a first direction and onto the device isolation region, and vertically overlapping with the channel region, the gate electrode having a first side surface and a second side surface opposite to each other in a second direction, perpendicular to the first direction; and a first blocking layer on a portion of the first source/drain region.