LDMOS Lightly-Doped Isolation Layer for High Breakdown Voltage
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Solution Overview
Problem
Conventional LDMOS devices face limitations in achieving high vertical breakdown voltage due to high doping in isolation layers, which restricts their high-side capability and increases manufacturing complexity and cost, especially when trying to support voltages above 30V.
Innovation Solution
The implementation of a lightly-doped isolation layer (LDIL) with doping less than 1e17 cm-3, which is depleted by surrounding layers to support a voltage drop between source and drain regions, allowing for higher vertical breakdown voltage without the need for additional epitaxial processes, thereby reducing manufacturing complexity and cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a heavily doped isolation layer is used to reduce parasitic BJT gain and increase punch-through voltage, then device reliability is improved, but vertical breakdown voltage is limited and manufacturing complexity increases
Solution Approach 1:
The patent changes the doping parameter of the isolation layer from heavy doping (conventional) to light doping (less than 1e17 atoms/cm³). This parameter change enables the isolation layer to be depleted by surrounding reverse polarity layers, supporting voltage drop laterally along the isolation layer and achieving high vertical breakdown voltage (>120V) without requiring complex epitaxial processes or additional sinker regions.
2Reliability
If high doping concentration is used in the isolation layer to support high voltage, then punch-through voltage is increased, but vertical breakdown voltage becomes a limiting factor
Solution Approach 1:
The patent applies parameter change by reducing the doping concentration of the isolation layer to less than 1e17 atoms/cm³. This light doping enables the isolation layer to be depleted by surrounding reverse polarity layers, allowing voltage to be supported laterally along the isolation layer rather than vertically at the junction, thereby achieving high vertical breakdown voltage (>120V) while maintaining adequate punch-through voltage.
3Adaptability or versatility
If conventional isolation layers are used to enable high-side capability, then device functionality is achieved, but additional epitaxial processes are required increasing manufacturing cost
Solution Approach 1:
The patent changes the doping parameter of the isolation layer to light doping (less than 1e17 atoms/cm³), which enables the isolation layer to support voltage drop laterally and achieve high vertical breakdown voltage. This eliminates the need for additional epitaxial growth processes or buried layer formations, thereby reducing manufacturing complexity and cost while maintaining high-side capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables LDMOS devices to achieve breakdown voltages greater than 120V, supporting high-side capability and reducing the need for complex epitaxial processes, while maintaining cost-effectiveness and efficient voltage management.
Implementation Method 1
The doping of the LDIL can cause the LDIL to be depleted by the surrounding layers of reverse polarity and supports a voltage drop between source and drain regions along the LDIL
Implementation Method 2
The exact doping is determined by providing charge balance between alternating p- and n-type layers for mutual depletion
Data Source
AI summary
An example laterally diffused metal oxide semiconducting (LDMOS) device includes a semiconductor substrate of a first conductivity type, active MOS regions, and a lightly-doped isolation layer (LDIL) of a second conductivity type. The active MOS regions include source and drain regions and a plurality of PN junctions. The LDIL is formed above and laterally along the semiconductor substrate, and located between the semiconductor substrate and at least a part of the active MOS regions. The LDIL is doped with dopant of the second conductivity type to cause, in response to selected voltages applied to the LDMOS device, the plurality of PN junctions to deplete each other and to support a voltage drop between the source and drain regions along the LDIL.