LDMOS Transistor with 3D Conductive Region for Reduced Cell Pitch
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Solution Overview
Problem
Conventional lateral double-diffused metal-oxide-semiconductor (LDMOS) transistors face limitations in miniaturization due to their relatively large cell pitch, necessitating a reduction in occupied area without compromising performance.
Innovation Solution
The semiconductor device incorporates trench structures and a conductive region with a 3D ring-shaped structure, featuring a buried layer, deep well, doped regions, and trench structures of varying depths to enhance carrier flow and reduce on-resistance, allowing for more compact high-voltage device design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS transistor structure is used, then high operational bandwidth and efficiency are achieved, but large cell pitch occupies excessive area
Solution Approach 1:
The patent introduces a vertical conductive region extending from the surface through the P-type well to the N-type buried layer, adding a vertical dimension to the current path. This 3D configuration reduces the lateral cell pitch while maintaining the high-voltage blocking capability and operational efficiency of conventional LDMOS structures.
Solution Approach 2:
The conductive region is nested within the P-type well structure, with the P-type region surrounding the vertical conductive path. This nested configuration allows the conductive region to be integrated within the existing transistor architecture without increasing the lateral footprint, thereby reducing cell pitch while preserving device performance.
2Reliability
If lateral diffused area is increased to buffer high voltage signals, then breakdown voltage is improved, but occupied area increases
Solution Approach 1:
The patent transitions from a lateral current buffering approach to a vertical current path by introducing a conductive region extending through the P-type well to the N-type buried layer. This vertical dimension provides an alternative current path that reduces the required lateral diffused area while maintaining high breakdown voltage capability.
Solution Approach 2:
The patent modifies the doping concentration parameters by creating a heavily doped N-type buried layer and configuring the P-type well with specific doping levels. These parameter changes enable the vertical conductive region to provide effective current buffering with reduced lateral dimensions, thereby reducing the occupied area while maintaining breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration minimizes power consumption and on-resistance, enabling more efficient high-voltage signal transmission and reducing the overall area occupied by DMOS transistor devices in semiconductor substrates.
Implementation Method 1
a conductive region having the first conductivity type being adjacent to the first doped region, wherein the conductive region has a doping concentration higher than the first doped region
Implementation Method 2
a first trench structure disposed in the semiconductor substrate at one side of the gate, wherein the first trench structure contacts the buried layer; and a second trench structure disposed in the semiconductor substrate at the other side of the gate opposite to the first trench structure
Data Source
AI summary
A semiconductor device includes a semiconductor substrate, a buried layer disposed in the semiconductor substrate; a deep well disposed in the semiconductor substrate; a first doped region disposed in the deep well, wherein the first doped region contacts the buried layer; a conductive region having the first conductivity type surrounding and being adjacent to the first doped region, wherein the conductive region has a concentration higher than the first doped region; a first heavily doped region disposed in the first doped region; a well having a second conductivity type disposed in the deep well; a second heavily doped region disposed in the well; a gate disposed on the semiconductor substrate between the first heavily doped region and the second heavily doped region; and a first trench structure and a second trench structure, wherein a depth of the second trench structure is substantially deeper than a depth of the buried layer.