Fin-Shaped LDMOS Gate Layout With Air Gaps for Leakage Control
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Solution Overview
Problem
Current LDMOS devices face challenges with current leakage and breakdown voltage control as the scale of devices decreases, particularly when integrated with FinFET devices, necessitating improved fabrication techniques to enhance performance.
Innovation Solution
The implementation of a lateral diffused metal oxide semiconductor (LDMOS) device design featuring fin-shaped structures, shallow trench isolation, and air gaps between gate structures to reduce parasitic capacitance and improve cut-off frequency and maximum oscillation frequency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device scale is decreased to improve integration density, then productivity increases, but current leakage increases and breakdown voltage control becomes difficult
Solution Approach 1:
The patent introduces air gaps in the vertical dimension between adjacent gate structures, transforming a two-dimensional planar layout into a three-dimensional structure with vertical separation. This dimensional change reduces parasitic capacitance and prevents current leakage paths while maintaining high integration density in the horizontal plane.
Solution Approach 2:
The air gap acts as an intermediary medium between adjacent gate structures, providing electrical isolation and reducing parasitic capacitance. This intermediary space prevents direct current leakage between gates while allowing the device to maintain compact dimensions.
2Productivity
If device scale is decreased to improve integration density, then productivity increases, but breakdown voltage control becomes difficult
Solution Approach 1:
By introducing vertical air gaps between gate structures, the patent creates additional spacing in the z-dimension that helps control electric field distribution. This dimensional change enables better breakdown voltage control even as horizontal dimensions are scaled down to improve integration density.
Solution Approach 2:
The patent modifies the structural parameters of the device by introducing air gaps with specific dimensions and positions. This changes the electric field distribution and capacitance characteristics, enabling breakdown voltage control to be maintained despite scaling down the overall device size.
3Speed
If air gaps are introduced between gate structures, then parasitic capacitance is reduced and cut-off frequency increases, but device complexity increases
Solution Approach 1:
The patent segments the gate structures by introducing air gaps between them, dividing what would be a continuous structure into discrete segments. This segmentation reduces parasitic capacitance and increases cut-off frequency, while the modular nature of the air gap formation simplifies the overall fabrication process.
Solution Approach 2:
The air gap introduces a porous or void structure between gate elements, utilizing the absence of material (air) to reduce parasitic capacitance. This approach achieves high-frequency performance without requiring complex additional materials or structures.
Data Source
AI summary
A lateral diffused metal oxide semiconductor (LDMOS) device includes a first fin-shaped structure on a substrate, a second fin-shaped structure adjacent to the first fin-shaped structure, a shallow trench isolation (STI) between the first fin-shaped structure and the second fin-shaped structure, a first gate structure on the first fin-shaped structure, a second gate structure on the second fin-shaped structure, and an air gap between the first gate structure and the second gate structure.