LDMOS Implant Alignment Spacers for Lower Gate Resistance
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Solution Overview
Problem
The gain and linearity of LDMOS transistors are compromised by parasitic feedback capacitance and high input impedance, which existing manufacturing processes struggle to control effectively due to precision issues in aligning implanted regions and increased gate resistance from scaling gate area.
Innovation Solution
A semiconductor manufacturing process involving the formation of conformal liners over a gate stack to offset implants and enable the creation of a thick, low-resistance Cobalt Silicide gate electrode, allowing for improved etching and implant alignment, thereby reducing feedback capacitance and input impedance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If photolithography alignment is used to position implanted regions, then manufacturing process simplicity is maintained, but alignment precision is insufficient to control feedback capacitance
Solution Approach 1:
The patent applies preliminary action by forming alignment spacers before the implantation process. The spacers are deposited and patterned in advance to define precise implantation regions, ensuring that the implanted regions are accurately positioned relative to the gate structure. This preliminary positioning structure enables sub-lithographic alignment precision without requiring more complex alignment tools or processes.
Solution Approach 2:
The alignment spacers serve as an intermediary element between the photolithography process and the implantation process. Rather than directly relying on photolithography to define implantation regions, the spacers act as a mediator that translates lithographic patterns into precisely positioned implantation masks, thereby decoupling the alignment precision requirements from the photolithography capabilities.
2Reliability
If gate area is scaled down to reduce input capacitance, then input impedance improves, but gate resistance increases
Solution Approach 1:
The patent applies parameter changes by modifying the gate electrode material composition and structure. Specifically, the gate electrode is formed with a composite structure including a first material and a second material with different electrical properties. By adjusting the thickness ratio, material selection, and spatial distribution of these two materials, the patent optimizes both the resistance and capacitance parameters simultaneously, achieving low input impedance while maintaining low gate resistance.
3Object-affected harmful factors
If gate metal thickness is increased to reduce gate resistance, then gate resistance decreases, but photolithography and etch process difficulty increases due to increased aspect ratio
Solution Approach 1:
The patent applies composite materials by forming the gate electrode as a multi-layer structure consisting of a first material layer and a second material layer. Each layer can be optimized for different functions: one layer for electrical conductivity (low resistance) and another for etch selectivity or mechanical stability. This composite approach allows achieving low gate resistance without requiring excessive thickness of a single material layer, thereby maintaining favorable aspect ratios for photolithography and etching.
4Area of stationary object
If implanted regions are positioned close to gate to reduce device area, then device area decreases, but parasitic feedback capacitance increases
Solution Approach 1:
The patent applies preliminary action by pre-forming alignment spacers that define the precise location of implanted regions before implantation occurs. These spacers are positioned to maintain optimal spacing between the implanted regions and the gate structure, ensuring that regions are close enough to minimize device area but far enough to reduce parasitic feedback capacitance. The spacer thickness and positioning are carefully controlled to achieve this optimal balance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This process enhances the gain and linearity of LDMOS transistors by precisely controlling drain and source profiles, enabling a thicker gate electrode with reduced resistance and improved aspect ratio etching, thus addressing the limitations of existing technologies.
Implementation Method 1
The gate stack is oxidized to form a polysilicon layer from the silicon layer
Implementation Method 2
A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer
Data Source
AI summary
A Laterally Diffused Metal Oxide Semiconductor (LDMOS) transistor with implant alignment spacers includes a gate stack comprising a first nitride layer. The first nitride layer is formed on a silicon layer. The gate stack is separated from a substrate by a first oxide layer. The gate stack includes a polysilicon layer formed from the silicon layer, and a second oxide layer is formed on a sidewall of the polysilicon layer. A drain region of the LDMOS transistor is implanted with a first implant aligned to a first edge formed by the second oxide layer. A second nitride layer conformingly covers the second oxide layer. A nitride etch-stop layer conformingly covers the second nitride layer.