LDMOS Transistor Angled Implant for Breakdown Voltage
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Solution Overview
Problem
Existing MOSFET transistors, such as LDMOS and VDMOS, face challenges in achieving optimal robustness and power density due to limitations in channel region width and doping levels, which affect their breakdown voltage and threshold voltage performance.
Innovation Solution
The use of an angled n-type implant in the p-body region of MOSFET transistors reduces the channel region width, thereby decreasing the peak doping level and increasing the on-state breakdown voltage and power density, while maintaining a targeted threshold voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the channel region width is reduced to increase breakdown voltage, then the on-state breakdown voltage increases, but the manufacturing precision required for the implant process increases
Solution Approach 1:
The patent applies preliminary action by forming the angled implant structure before final device fabrication steps. The n-type implant is performed at a predetermined angle (e.g., 45 degrees) relative to the surface during earlier processing stages, establishing the channel width modulation geometry in advance. This preliminary structuring allows subsequent processing to proceed with standard precision requirements while the pre-formed angled implant provides the desired breakdown voltage enhancement.
2Strength
If the peak doping level is decreased to increase breakdown voltage, then the on-state breakdown voltage increases, but the device productivity decreases
Solution Approach 1:
The patent applies local quality by creating spatially varying doping characteristics through the angled implant geometry. The n-type implant at an angle creates a non-uniform doping profile where the peak doping level is reduced in the critical channel region while maintaining adequate doping in other areas. This localized doping optimization achieves enhanced breakdown voltage without requiring comprehensive reduction of doping levels throughout the entire device structure, thereby avoiding productivity loss.
3Power
If the channel region width is reduced to increase power density, then the maximum power density increases, but the manufacturing complexity increases
Solution Approach 1:
The patent applies asymmetry by using an angled implant approach that creates an asymmetric doping profile relative to the device geometry. The n-type implant is introduced at a specific angle (e.g., 45 degrees) rather than perpendicular to the surface, creating an asymmetric concentration distribution that effectively modulates the channel width. This asymmetric implant strategy achieves power density enhancement without requiring complex multi-step implantation sequences or sophisticated mask patterns, thereby limiting the increase in manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the robustness and power handling capacity of MOSFET transistors by increasing the on-state breakdown voltage and maximum power density without compromising the threshold voltage.
Implementation Method 1
an angled n-type implant in a p-body region of the MOSFET transistor
Implementation Method 2
decreasing the peak doping level and increasing the on-state breakdown voltage and power density
Data Source
AI summary
A LDMOS transistor having a channel region located between an outer boundary of an n-type region and an inner boundary of a p-body region. A width of the LDMOS channel region is less than 80% of a distance between an outer boundary of an n+-type region and the inner boundary of a p-body region. Also, a method for making a LDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants. Furthermore, a VDMOS having first and second channel regions located between an inner boundary of a first and second p-body region and an outer boundary of an n-type region of the first and second p-body regions. The width of the first and second channel regions of the VDMOS is less than 80% of a distance between the inner boundary of the first and second p-body regions and an outer boundary of an n+-type region of the first and second p-body regions. Moreover, a method for making a VDMOS transistor where the n-type dopants are implanted at an angle that is greater than an angle used to implant the p-type dopants.