LDMOS Transistor Array Misalignment Monitoring
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Solution Overview
Problem
LDMOS transistor arrays face misalignment biases during manufacturing, leading to asymmetric device operation, increased series on-resistance, substrate current, and reduced hot carrier reliability, which degrade device performance and lead to early failure.
Innovation Solution
A method is introduced to monitor and minimize process misalignment biases by forming modified LDMOS transistor arrays with separate gate connections, allowing each device to be monitored separately, and conducting tests to quantify asymmetries in substrate currents, series on-resistances, and breakdown voltages, thereby adjusting mask alignment to ensure symmetrical operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If separate gate connections are implemented to monitor each device separately, then measurement precision of device asymmetries is improved, but device complexity increases
Solution Approach 1:
The patent segments the gate structure by providing separate gate connections (first gate connection and second gate connection) for each MOS device instead of a shared connection. This segmentation enables independent electrical characterization of each device, allowing precise measurement of asymmetries in substrate current, series on-resistance, and breakdown voltage between the first and second MOS devices while maintaining manageable device complexity through systematic testing procedures
2Reliability
If process misalignment biases are eliminated through monitoring, then reliability of LDMOS devices is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent implements a feedback mechanism where electrical characteristics (substrate current, series on-resistance, breakdown voltage) are measured and compared between the first and second MOS devices. The system determines whether asymmetries exceed predetermined thresholds and provides feedback to adjust the relative alignment between the first and second n- drain extension regions. This feedback loop enables continuous monitoring and correction of process misalignment biases, improving reliability while managing manufacturing precision through adaptive adjustment rather than requiring perfect initial alignment
3Reliability
If asymmetric device operation is reduced by adjusting mask alignment, then hot carrier reliability is improved, but manufacturing time increases
Solution Approach 1:
The patent performs preliminary electrical characterization of each MOS device using the separate gate connections before final assembly or operation. By measuring substrate current, series on-resistance, and breakdown voltage early in the manufacturing process, the system can identify and correct alignment issues before they propagate to final product performance. This preliminary action reduces the need for time-consuming iterative adjustments later, improving hot carrier reliability while minimizing overall manufacturing time loss
Data Source
AI summary
A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.