LDMOS Transistor with Asymmetric Gate Oxide for Low Loss Switching
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Solution Overview
Problem
Switching regulators in low power devices, such as laptop notebooks and cellular phones, face efficiency losses due to reverse recovery of intrinsic body diodes during deadtime and diode conduction in switching regulators, which are exacerbated by the high turn-on voltage of traditional transistors.
Innovation Solution
A lateral double-diffused metal oxide semiconductor (LDMOS) transistor with a gate oxide layer having a thin side and a thicker side, where the thin side's turn-on voltage is less than 0.6V, reducing the recovery time and conduction losses by allowing current to flow through the transistor instead of the body diode during deadtime.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If traditional transistors with high turn-on voltage are used in switching regulators, then the transistor can block higher voltages, but reverse recovery losses and conduction losses increase during deadtime
Solution Approach 1:
The gate oxide layer is designed with non-uniform thickness, having a first thickness in the first region and a second thickness in the second region. This local variation in oxide thickness creates different turn-on voltages in different regions of the transistor, allowing the transistor to have low turn-on voltage for efficient conduction while maintaining overall voltage blocking capability through the thicker oxide regions.
2Ease of operation
If the gate oxide layer has uniform thickness, then the manufacturing process is simpler, but the transistor cannot achieve both low turn-on voltage and high voltage blocking capability
Solution Approach 1:
The gate oxide layer is segmented into different thickness regions - a first region with a first thickness and a second region with a second thickness. This segmentation allows different portions of the transistor to perform different functions: one region optimized for low turn-on voltage while another region maintains voltage blocking capability, resolving the contradiction between operational ease and device complexity.
3Loss of energy
If the transistor allows current flow during deadtime, then conduction losses are reduced, but the transistor must have lower turn-on voltage than traditional designs
Solution Approach 1:
The turn-on voltage parameter is modified by changing the gate oxide thickness. By making the gate oxide thinner in the first region, the turn-on voltage is reduced, allowing the transistor to conduct during deadtime with lower voltage threshold. This parameter change enables current flow during deadtime, reducing conduction losses while maintaining controllability through the thicker oxide regions.
Data Source
AI summary
A transistor includes a source region including a first impurity region implanted into a substrate, a drain region including a second impurity region implanted into the substrate, and a gate including an oxide layer formed over the substrate and a conductive material formed over the oxide layer, the oxide layer comprising a first side and a second side, the first side formed over a portion of the first impurity region and the second side formed over a portion of the second impurity region, the first side having a thickness of less than about 100 Å, and the second side having a thickness equal to or greater than 125 Å.