LDMOS Back Gate Region Placement for Parasitic Bipolar Suppression
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Solution Overview
Problem
High breakdown voltage LDMOS devices with trench gate and back gate structures suffer from parasitic bipolar operations, leading to low on-state breakdown voltage due to increased potential in the p-type body region, which cannot be fully reduced by the back gate region.
Innovation Solution
A semiconductor device with a back gate region arranged between first and second portions of a source region, positioned closer to the drain region, effectively reducing the potential in the p-type body region and suppressing parasitic bipolar operations by optimizing the placement and impurity density of the back gate region.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a back gate region is arranged on a side opposite to the drain region with respect to the source region, then the structure is simplified, but the potential in the p type body region cannot be fully reduced, causing low on-state breakdown voltage
Solution Approach 1:
The source region is divided into first and second portions, and the back gate region is positioned between them rather than surrounding the entire source region. This segmented arrangement allows the back gate region to effectively reduce potential in the p type body region while maintaining structural simplicity.
Solution Approach 2:
The back gate region is strategically positioned between the first and second portions of the source region, creating a localized electric field that specifically addresses the potential increase in the p type body region during large current operation, thereby suppressing parasitic bipolar operation in the critical area.
2Ease of manufacture
If the back gate region is positioned farther from the drain region, then the manufacturing process is simplified, but parasitic bipolar operation occurs due to insufficient potential reduction in the p type body region
Solution Approach 1:
The back gate region is positioned between the first and second portions of the source region, creating a localized electric field that specifically addresses the potential increase in the p type body region during large current operation, thereby suppressing parasitic bipolar operation in the critical area.
Solution Approach 2:
The position of the back gate region is optimized to be between the first and second portions of the source region and closer to the drain region, changing the spatial parameter to achieve effective potential reduction without excessive manufacturing complexity.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration improves the on-state breakdown voltage by reducing parasitic bipolar operations and enhancing depletion layers, resulting in increased breakdown voltage and reduced on-state resistance.
Implementation Method 1
a back gate region is arranged in a main surface between first and second portions of a first impurity region, and arranged on a side closer to a second impurity region with respect to the first impurity region
Implementation Method 2
enhancing depletion layers, resulting in increased breakdown voltage
Data Source
AI summary
In a semiconductor device, a p+ back gate region (PBG) is arranged in a main surface (S1) between first and second portions (P1, P2) of an n+ source region (SR), and arranged on a side closer to an n+ drain region (DR) with respect to the n+ source region (SR). Thereby, a semiconductor device having a high on-state breakdown voltage can be obtained.