LDMOS Transistor Backside Field Plate for SOI Reliability
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Solution Overview
Problem
LDMOS transistors fabricated on SOI substrates suffer from reliability issues that prevent achieving the full performance potential offered by SOI technology, due to parasitic capacitance and hot carrier effects, which degrade device performance and limit breakdown voltage.
Innovation Solution
The integration of a backside device, such as a field plate, formed using layer transfer technology on a semiconductor on insulator (SOI) layer, which reduces gate-to-drain capacitance and mitigates hot carrier effects by controlling the electric field and charge movement, enabling higher breakdown voltage and lower on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If LDMOS transistors are fabricated on SOI substrates, then parasitic capacitance is reduced and performance is improved, but reliability issues arise due to hot carrier effects and insufficient breakdown voltage
Solution Approach 1:
The patent introduces a backside field plate structure that extends the field control into the vertical dimension beneath the SOI substrate. By placing a field plate on the backside of the substrate and connecting it to the gate, the electric field distribution is controlled in three dimensions, effectively reducing hot carrier effects and parasitic capacitance while improving breakdown voltage without compromising device reliability
Solution Approach 2:
The patent introduces an intermediary layer (buried oxide layer) between the active device and the substrate, and further uses a backside field plate as a mediating structure to control the electric field. This intermediary approach allows the device to benefit from reduced parasitic capacitance while the field plate mediates the electric field to prevent hot carrier injection, resolving the reliability issue
2Object-affected harmful factors
If BOX layer thickness is reduced to reduce parasitic capacitance, then capacitance decreases, but hot carrier effects increase and reliability deteriorates
Solution Approach 1:
Instead of only reducing BOX thickness in the vertical dimension, the patent adds a backside field plate structure that extends field control to the third dimension (beneath the substrate). This dimensional extension allows maintaining adequate BOX thickness for reliability while still achieving low parasitic capacitance through the field plate's electric field control
Solution Approach 2:
The backside field plate is positioned and biased to preemptively counteract the formation of high electric fields that would cause hot carrier effects. By applying a preliminary opposing electric field through the field plate, the patent prevents hot carrier injection before it occurs, maintaining reliability even with reduced BOX thickness
3Power
If LDMOS structure is used to achieve low on-resistance and high blocking voltage, then power handling capability is improved, but hot carrier effects and reliability issues worsen
Solution Approach 1:
The backside field plate extends the field control into the vertical dimension beneath the device, creating a three-dimensional electric field management system. This allows the LDMOS structure to maintain its high power handling capability through low on-resistance while the backside field plate simultaneously controls electric field distribution to prevent hot carrier effects, resolving the reliability issue
Solution Approach 2:
The patent applies different electric field control strategies to different regions: the frontside gate controls the channel formation for low on-resistance, while the backside field plate locally controls the electric field beneath the drain region to prevent hot carrier effects. This localized quality control allows high power handling while maintaining reliability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows LDMOS transistors to realize the full performance potential of SOI technology by reducing parasitic capacitance and enhancing breakdown voltage, while maintaining low on-resistance, thus improving the reliability and performance of mobile RF transceivers.
Implementation Method 1
mitigates hot carrier effects by controlling the electric field and charge movement
Implementation Method 2
reduces parasitic device capacitance and improving performance
Data Source
AI summary
An integrated circuit is described. The integrated circuit includes a laterally diffused metal oxide semiconductor (LDMOS) transistor. The LDMOS is on a first surface of an insulator layer of the integrated circuit. The LDMOS transistor includes a source region, a drain region, and a gate. The LDMOS transistor also includes a secondary well between the drain region and the gate. The secondary well has an opposite polarity from the drain region. The LDMOS transistor further includes a backside device on a second surface opposite the first surface of the insulator layer.