LDMOS Field Oxide Bevel Structure for Higher Breakdown Voltage
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Solution Overview
Problem
The formation of sharp corners during the local oxidation of silicon (LOCOS) process in LDMOS devices leads to charge accumulation, reducing the breakdown voltage and integrity of the field oxide layer, resulting in reliability issues.
Innovation Solution
A bevel structure is formed by creating a stair-step insulating layer with a controlled angle between 45° and 60° using multiple etching processes and wet etching to smooth the corners, reducing charge accumulation and enhancing the breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LOCOS process is used to form field oxide layer, then the insulation performance is improved, but sharp corners are formed causing charge accumulation that reduces breakdown voltage
Solution Approach 1:
The patent applies curvature by forming a bevel structure with rounded corners instead of sharp corners at the field oxide layer edges. This curvature eliminates the charge accumulation points that occur at sharp corners, thereby maintaining insulation performance while preventing breakdown voltage reduction.
Solution Approach 2:
The bevel structure is formed preliminarily during the LOCOS process before final device operation. By pre-shaping the field oxide layer edges with a controlled bevel angle (45-60 degrees), the structure prevents charge accumulation from occurring in the first place, rather than attempting to remove it later.
2Reliability
If multiple etching processes are used to form bevel structure, then the breakdown voltage is improved, but the manufacturing complexity increases
Solution Approach 1:
The bevel structure formation is segmented into multiple etching steps with different angles. The first etching process creates a preliminary bevel at a first angle, and the second etching process refines it to the final angle (45-60 degrees). This segmentation allows precise control of the bevel geometry to optimize breakdown voltage while keeping each individual etching step relatively simple.
Solution Approach 2:
The patent changes geometric parameters by forming bevel structures with specific angle ranges (45-60 degrees) through controlled etching processes. By optimizing these angular parameters, the breakdown voltage is enhanced while the manufacturing complexity is managed through standardized angular specifications that can be replicated.
3Reliability
If the field oxide layer is made thicker to improve insulation, then the insulation performance is improved, but the device area increases
Solution Approach 1:
Instead of uniformly thickening the field oxide layer across the entire device, the patent applies local quality by forming a bevel structure specifically at the critical edge regions where charge accumulation occurs. This localized structural modification improves insulation performance at the problem areas without increasing the overall device area.
Solution Approach 2:
The patent addresses the insulation problem by transitioning from a two-dimensional thickness parameter to a three-dimensional bevel structure. By creating angled surfaces and rounded corners in the third dimension, the field oxide layer maintains its insulating function while avoiding the need for uniform thickness increases that would expand the device footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The bevel structure improves the uniformity of electric field distribution and increases the breakdown voltage of semiconductor devices by reducing charge accumulation and ensuring the integrity of the high-voltage oxide layer.
Implementation Method 1
wet etching to smooth the corners
Data Source
AI summary
A method of making a bevel structure can include: forming an insulating layer on a substrate; forming a first photoresist layer on the insulating layer; performing an exposure and development process on the first photoresist layer to form a second photoresist layer; using the second photoresist layer as a mask to perform a first etching process from an upper surface of the exposed insulating layer until the upper surface of the substrate is exposed; removing part of a first side of the second photoresist layer to continuously expose the upper surface of the insulating layer; using a retained portion of the second photoresist layer as a mask to perform a second etching process from the upper surface of the exposed insulating layer to inside the insulation layer to form a stair-step insulating layer with decreasing length; and wet etching the stair-step insulating layer to form a smooth bevel structure.