LDMOS Body Diffusion Self-Aligned to Gate
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Solution Overview
Problem
Conventional LDMOS devices face challenges in reducing switching parasitics Qgate and Cdrain, and area-normalized ON-state resistance RSP, due to misalignment and long DWELL diffusion times, which limit their performance and efficiency in next-generation power converter applications.
Innovation Solution
A self-aligned DWELL process is introduced, where the DWELL p-type implant is aligned with the gate electrode, reducing the effective channel length (LEFF) to 75 nm to 150 nm, and incorporating a rapid thermal anneal to activate dopants and improve breakdown voltage, thereby reducing parasitics and ON-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional DWELL process with masked boron body implant is used, then the process flow is established, but misalignment between DWELL diffusions and gate electrode occurs resulting in long effective channel length (≥500 nm)
Solution Approach 1:
The gate electrode serves as its own alignment reference for the DWELL implant. By using the gate electrode edge as the mask boundary, the process achieves self-alignment, eliminating the need for separate mask alignment steps and reducing effective channel length to 75-150 nm.
Solution Approach 2:
The gate electrode is formed first before the DWELL implant process. This preliminary formation of the gate structure provides the reference geometry that defines the precise location where the DWELL implant should occur, ensuring accurate alignment.
2Stability of the object's composition
If long furnace anneals and MeV boron buried layer implant are used, then laterally graded p-body doping profile is achieved, but the process complexity and time increase
Solution Approach 1:
The patent changes the implant energy parameter from MeV (million electron volts) to keV (thousand electron volts) range, and modifies the annealing parameters to achieve the desired doping profile more quickly. This parameter optimization reduces process time while maintaining the laterally graded p-body doping profile.
Solution Approach 2:
The patent eliminates the need for long furnace anneals by using optimized rapid thermal processing. The dopant activation and diffusion are achieved in significantly reduced time by skipping the conventional lengthy thermal treatment steps.
3Loss of energy
If effective channel length is reduced to 75 nm to 150 nm, then parasitics Qgate and Cdrain are reduced, but manufacturing precision requirements increase
Solution Approach 1:
The gate electrode automatically defines the implant boundaries through its physical presence as the mask edge. This self-service alignment mechanism ensures that even with sub-150 nm effective channel length, the alignment precision is maintained because the gate structure itself serves as the reference.
Solution Approach 2:
The gate electrode acts as an intermediary between the lithography mask and the implant process. By using the gate edge as the defining boundary, it mediates the alignment between different process steps, enabling precise control of the effective channel length.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The self-aligned DWELL process significantly reduces Qgate, Cdrain, and RSP, enhancing the performance of LDMOS devices by improving current drive and reducing power loss, while maintaining low power dissipation and efficient area utilization.
Implementation Method 1
incorporating a rapid thermal anneal to activate dopants and improve breakdown voltage
Implementation Method 2
DWELL p-type implant is aligned with the gate electrode
Data Source
AI summary
A laterally diffused metal oxide semiconductor (LDMOS) device includes a substrate having a p-epi layer thereon, a p-body region in the p-epi layer and an ndrift (NDRIFT) region within the p-body to provide a drain extension region. A gate stack includes a gate dielectric layer over a channel region in the p-body region adjacent to and on respective sides of a junction with the NDRIFT region. A patterned gate electrode is on the gate dielectric. A DWELL region is within the p-body region. A source region is within the DWELL region, and a drain region is within the NDRIFT region. An effective channel length (Leff) for the LDMOS device is 75 nm to 150 nm which evidences a DWELL implant that utilized an edge of the gate electrode to delineate an edge of a DWELL ion implant so that the DWELL region is self-aligned to the gate electrode.