LDMOS Transistor Body Tie Merging for Reduced On-Resistance
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Solution Overview
Problem
Conventional LDMOS transistors have an increased footprint due to the body tie region, which also raises the on-resistance and area product, posing a challenge in reducing the parasitic bipolar transistor's activation and potentially damaging the transistor.
Innovation Solution
The solution involves situating body tie regions adjacent to the gate and source regions, reducing the distance between them, and using a silicide layer to electrically connect body tie and source regions, thereby reducing parasitic resistance and area while maintaining control over the parasitic bipolar transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a body tie region is situated close to the source region to reduce resistance, then the on-resistance is reduced, but the area or footprint of the MOS transistor increases
Solution Approach 1:
The body tie region is merged with the source region by forming the body tie region within the source region boundaries. This integration allows the body tie contact to electrically connect the source region to the body region while occupying the same physical space as the source region, thereby reducing resistance without increasing the transistor footprint.
Solution Approach 2:
The body tie region is positioned in a vertical dimension within the source region rather than extending horizontally adjacent to it. This dimensional repositioning allows the body tie contact to be formed through the source region to reach the body region, achieving electrical connection without increasing the planar footprint of the device.
2Reliability
If the body tie region is extended to reduce parasitic resistance, then the electrical connection is improved, but the device area increases
Solution Approach 1:
The body tie region is merged with the source region by forming the body tie region within the source region boundaries. This integration allows the body tie contact to electrically connect the source region to the body region while occupying the same physical space as the source region, thereby reducing resistance without increasing the transistor footprint.
3Reliability
If the body tie region is positioned to control the parasitic bipolar transistor, then the transistor protection is improved, but the footprint increases
Solution Approach 1:
The body tie region is merged with the source region by forming the body tie region within the source region boundaries. This integration allows the body tie contact to electrically connect the source region to the body region while occupying the same physical space as the source region, thereby reducing resistance without increasing the transistor footprint.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration results in a reduced on-resistance and area product for the MOS transistor, enhancing control over the parasitic bipolar transistor and minimizing the transistor's footprint on the semiconductor die.
Implementation Method 1
using a silicide layer to electrically connect body tie and source regions, thereby reducing parasitic resistance
Data Source
AI summary
According to an exemplary embodiment, a MOS transistor, such as an LDMOS transistor, includes a gate having a first side situated immediately adjacent to at least one source region and at least one body tie region. The MOS transistor further includes a drain region spaced apart from a second side of the gate. The MOS transistor further includes a body region in contact with the at least one body tie region, where the at least one body tie region is electrically connected to the at least one source region. The MOS transistor further includes a lightly doped region separating the drain region from the second side of the gate. The lightly doped region can isolate the body region from an underlying substrate.