LDMOS Transistor Bootstrap Charging Circuit
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Solution Overview
Problem
The complexity of the source potential control circuit and back gate potential control circuit in semiconductor devices increases manufacturing costs by requiring additional circuitry to prevent parasitic transistor operation during bootstrap capacitor charging.
Innovation Solution
A semiconductor device configuration that includes a high breakdown voltage N-channel MOS transistor with a source electrode and back gate electrode connected in a manner that allows charging of the bootstrap capacitor without additional control circuits, using a power supply voltage greater than the back gate electrode, which is grounded, to simplify the circuit and prevent parasitic transistor operation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If source potential control circuit and back gate potential control circuit are connected to prevent parasitic transistor operation, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent extracts and eliminates the complex source potential control circuit and back gate potential control circuit from the semiconductor device. Instead of using these separate control circuits, the invention uses the inherent structure of the LDMOS transistor with properly configured semiconductor regions and electrodes to naturally prevent parasitic transistor operation, thereby reducing overall device complexity while maintaining reliability
Solution Approach 2:
The LDMOS transistor structure is designed to self-regulate and prevent parasitic transistor operation through its inherent semiconductor region configurations. The first, second, and third semiconductor regions with specific conductivity types automatically control the potentials to prevent parasitic conduction, eliminating the need for external control circuits
2Reliability
If additional control circuits are added to prevent parasitic transistor operation, then reliability is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent removes the need for additional control circuits by utilizing the inherent capabilities of the LDMOS transistor structure. The semiconductor regions are configured during the standard manufacturing process to automatically prevent parasitic transistor operation, thereby reducing manufacturing complexity and cost while maintaining reliability
Solution Approach 2:
The LDMOS transistor structure performs multiple functions: it serves as the main switching device, charges the bootstrap capacitor, and simultaneously prevents parasitic transistor operation through its inherent semiconductor region configuration. This multi-functionality eliminates the need for separate control circuits, simplifying manufacturing
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration reduces manufacturing costs by eliminating the need for complex control circuits and enhances the reliability of the semiconductor device by preventing parasitic transistor operation, allowing for efficient charging of the bootstrap capacitor.
Implementation Method 1
The gate electrode is arranged to face a channel region located in the second semiconductor region between the third semiconductor region and the first semiconductor region with a gate insulating film interposed therebetween
Implementation Method 2
The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage
Data Source
AI summary
The semiconductor device that supplies a charging current to a bootstrap capacitor includes a semiconductor layer, an N+-type diffusion region, an N-type diffusion region, a P+-type diffusion region, a P-type diffusion region, an N+-type diffusion region, a source electrode, a drain electrode, a back gate electrode, and a gate electrode. The N+-type diffusion region and the N-type diffusion region are electrically connected to a first electrode of the bootstrap capacitor. The N+-type diffusion region is supplied with a power supply voltage. The source electrode is connected to the N+-type diffusion region and is supplied with the power supply voltage. The back gate electrode is connected to a region separated from the N+-type diffusion region and is grounded. The breakdown voltage between the source electrode and the back gate electrode is greater than the power supply voltage.