LDMOS Transistor with Bottom Gate and Ballast Drift
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Solution Overview
Problem
Conventional LDMOS designs fail to provide a complete solution for short channel devices with small pitch size for high voltage applications, as they increase specific resistance and device size while struggling to support efficient high frequency operation with low RDSON and Q.
Innovation Solution
The design incorporates a gate structure with a tapered body region implanted in a substrate, a source region adjacent the channel, and a drain region laterally spaced from the gate, along with a drift region extending over a buried layer, featuring a JFET region with a voltage-controlled bottom gate to manage electric field distribution, allowing high-voltage operation without significant process cost or device size increase.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the lateral drift region is extended to accommodate higher voltages, then the voltage handling capability is improved, but the triode region on-state resistance RDSON and device size increase
Solution Approach 1:
The drift region is segmented into multiple doping regions with different doping concentrations. The lightly doped drift region handles high voltage breakdown, while heavily doped regions (such as the n+ drift region and drain extension) are positioned to reduce on-state resistance by providing low-resistance current paths when the device is conducting.
Solution Approach 2:
Different regions of the drift structure are assigned different doping qualities: the main drift region is lightly doped for high voltage capability, while localized regions (drain extension, n+ drift region) are heavily doped to reduce resistance. This local quality differentiation allows simultaneous optimization of both voltage handling and conduction characteristics.
2Use of energy by moving object
If split or stepped poly gates are used to minimize main gate area, then the gate charge Qg is reduced, but device size and output capacitance increase
Solution Approach 1:
The gate structure is extracted into multiple independently controllable gates (first gate and second gate) that can be optimized separately. The first gate controls the main channel for low gate charge operation, while the second gate controls the drain extension region, allowing independent optimization of gate areas and reducing total device size compared to conventional split gate structures.
3Strength
If conventional LDMOS designs are used, then high voltage operation is supported, but specific resistance and device complexity increase for short channel devices
Solution Approach 1:
The LDMOS structure is merged with JFET characteristics by forming a pn junction between the p-body region and the n+ drift region. This merged structure combines the high voltage capability of LDMOS with the low resistance characteristics of JFET, reducing specific resistance while maintaining high voltage operation and simplifying the device structure.
Solution Approach 2:
The device employs composite doping structures combining p-type and n-type regions in specific configurations. The p-body/n+ drift region junction creates a pn junction that provides both high voltage blocking capability and low resistance conduction path, effectively creating a composite functional structure that outperforms conventional single-type doping approaches.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables short channel extended drain devices to operate at high voltages with reduced specific resistance and switching loss, facilitating efficient high-frequency operation using a single thin gate oxide thickness, while minimizing process complexity and cost.
Implementation Method 1
The JFET region provides a voltage controlled bottom gate to control the electric field distribution between the JFET region and a ballast drift portion of the first highly doped drift region portion under the isolation structure
Implementation Method 2
LDMOS transistors include a lightly doped lateral diffused drain region between the heavily doped drain contact and the transistor channel to conduct lateral current and form a depletion region to create a voltage drop between the drain contact and the transistor gate
Data Source
AI summary
Disclosed examples include LDMOS transistors and integrated circuits with a gate, a body region implanted in the substrate to provide a channel region under a portion of the gate, a source adjacent the channel region, a drain laterally spaced from a first side of the gate, a drift region including a first highly doped drift region portion, a low doped gap drift region above the first highly doped drift region portion, and a second highly doped region portion above the gap drift region, and an isolation structure extending through the second highly doped region portion into the gap drift region portion, with a first end proximate the drain region and a second end under the gate dielectric layer, where the body region includes a tapered side laterally spaced from the second end of the isolation structure to define a trapezoidal JFET region.