LDMOS Transistor Breakdown Voltage via Isolated Conductor Leads
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Solution Overview
Problem
High voltage LDMOS transistors suffer from low breakdown voltages at curved regions due to electric field crowding effects, which are exacerbated by existing methods to increase breakdown voltage that often result in undesirable increases in on-state resistance.
Innovation Solution
The implementation of a trapped-drain configuration in LDMOS transistors, where the drain region is enclosed by the gate, and the use of isolated conductor leads between the gate and drain, reduces electric field effects at the drain tip without adding additional processing steps or masks, thereby increasing breakdown voltage without increasing on-state resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Shape
If the layout geometry of an LDMOS transistor includes curved regions, then the transistor can be formed in loops or oval configurations, but the breakdown voltage is reduced due to electric field crowding effects at the curved regions
Solution Approach 1:
The patent applies local quality by introducing field oxide regions specifically at curved regions of the LDMOS transistor layout. These field oxide regions are positioned where electric field crowding occurs, providing localized field control without altering the overall curved layout geometry. This allows the transistor to maintain its desired shape while improving breakdown voltage characteristics at critical curved regions.
2Reliability
If approaches are used to reduce electric field crowding at curved regions by altering dimensions of transistor features, then breakdown voltage may improve, but variations in device performance are introduced and device characteristics are altered
Solution Approach 1:
The patent introduces field oxide regions as intermediary structures between the curved layout geometry and the electric field. These field oxide regions act as mediators that reduce electric field crowding effects without requiring dimensional changes to the transistor features. This intermediary approach maintains consistent device dimensions while still improving breakdown voltage, thereby reducing performance variations.
3Reliability
If the breakdown voltage is increased, then the transistor can handle higher voltages, but the on-state resistance increases which is undesirable for high-voltage applications
Solution Approach 1:
The patent segments the field control function by introducing separate field oxide regions at curved regions, distinct from the main transistor structure. This segmentation allows independent optimization of breakdown voltage at curved regions without affecting the on-state resistance characteristics of the main transistor channel. The field oxide regions provide localized field management that improves breakdown voltage while maintaining low on-state resistance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively increases breakdown voltage, as demonstrated by raising it from 800 V to 950 V, specifically at the drain tip, while maintaining low on-state resistance, thus optimizing device performance across the entire layout geometry.
Implementation Method 1
the LDMOS transistor can suffer from a low breakdown voltage at the curved regions due to electric field crowding effects. Electric field crowding effects describe the conditions where the surface electric field of an LDMOS transistor is higher at the curved regions of the transistor
Data Source
AI summary
A lateral DMOS transistor is provided with a source region, a drain region, and a conductive gate. The drain region is laterally separated from the conductive gate by a field oxide that encroaches beneath the conductive gate. The lateral DMOS transistor may be formed in a racetrack-like configuration with the conductive gate including a rectilinear portion and a curved portion and surrounded by the source region. Disposed between the conductive gate and the trapped drain is one or more levels of interlevel dielectric material. One or more groups of isolated conductor leads are formed in or on the dielectric layers and may be disposed at multiple device levels. The isolated conductive leads increase the breakdown voltage of the lateral DMOS transistor particularly in the curved regions where electric field crowding can otherwise degrade breakdown voltages.