LDMOS Buffer Dielectric Layout for Lower Current Crowding
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Solution Overview
Problem
Current laterally-diffused metal-oxide-semiconductor (LDMOS) devices face challenges in reducing current crowding at the corners of field oxide layers and top layers, which affects their specific on-resistance and breakdown voltage performance, especially in high-voltage applications.
Innovation Solution
A structure and method for forming a laterally-diffused metal-oxide-semiconductor device with a buffer dielectric layer having varying thickness sections and a gate electrode configuration that reduces current crowding by strategically positioning doped regions and dielectric layers, allowing for improved voltage handling and on-resistance characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a thick field oxide layer is used to increase breakdown voltage, then breakdown voltage is improved, but current crowding occurs at the corners of the field oxide layer
Solution Approach 1:
The buffer dielectric layer is configured with different thicknesses in different regions: a first thickness in the first region and a second thickness (greater than the first) in the second region adjacent to the drain. This local variation in dielectric thickness allows the structure to simultaneously maintain high breakdown voltage (through the thicker buffer layer near the drain) and reduce current crowding (through the thinner buffer layer in other regions), thereby resolving the technical contradiction.
Solution Approach 2:
The invention changes the parameter of buffer dielectric layer thickness from uniform to non-uniform. By adjusting the thickness parameter spatially (thinner in the first region, thicker in the second region adjacent to the drain), the structure optimizes both breakdown voltage and current distribution, eliminating current crowding while maintaining high voltage handling capability.
2Ease of manufacture
If the buffer dielectric layer has uniform thickness, then manufacturing is simplified, but current crowding cannot be effectively reduced
Solution Approach 1:
The buffer dielectric layer is designed with local quality variation, having different thicknesses in different regions. This spatially varying thickness profile is specifically engineered to redirect current flow and reduce crowding at critical areas, while still being manufacturable using standard semiconductor fabrication techniques such as selective epitaxial growth or chemical vapor deposition with patterned masking.
3Reliability
If a top layer is added to decrease specific on-resistance, then specific on-resistance is improved, but current crowding increases at the corners
Solution Approach 1:
The buffer dielectric layer's non-uniform thickness configuration works in conjunction with the top layer to locally manage current flow. The varying thickness allows current to be redistributed in regions where the top layer is present, reducing the harmful corner effects while maintaining the low on-resistance benefit provided by the top layer structure.
Solution Approach 2:
The buffer dielectric layer acts as an intermediary structure between the drift region and the field oxide layer. Its non-uniform thickness profile mediates the interaction between the top layer and the field oxide, allowing current to flow more uniformly by providing a thickness gradient that reduces the sharp field concentration at corners, thereby reducing current crowding while maintaining low on-resistance.
Data Source
AI summary
Structures for a laterally-diffused metal-oxide-semiconductor device and methods of forming a structure for a laterally-diffused metal-oxide-semiconductor device. The structure includes a drift well in a semiconductor substrate, source and drain regions in the semiconductor substrate, a gate dielectric layer on the semiconductor substrate, and a buffer dielectric layer on the semiconductor substrate over the drift well. The buffer dielectric layer includes a first side edge adjacent to the drain region, a second side edge adjacent to the gate dielectric layer, a first section extending from the second side edge to the first side edge, and a plurality of second sections extending from the second side edge toward the first side edge. The first section has a first thickness, and the second sections have a second thickness less than the first thickness. A gate electrode includes respective portions that overlap with the buffer dielectric layer and with the gate dielectric layer.