LDMOS Buried Diffusion Area Mitigates Gate Edge Field Stress
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Solution Overview
Problem
Conventional LDMOS transistors face challenges in achieving both low on-resistance and high withstand voltage simultaneously due to tradeoffs between these two factors, and existing methods require complex control mechanisms and high-energy ion implantation processes that are costly and unstable.
Innovation Solution
A semiconductor device configuration where a buried diffusion area of the first conductivity type extends beneath the drain area, mitigating electrical fields at the gate edge and allowing higher drift area concentration without the need for precise taper angle control, and an optional auxiliary diffusion area ensures equal potential between the drain and well areas, reducing on-resistance and maintaining high withstand voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If conventional ion implantation methods are used to form buried diffusion areas, then withstand voltage can be improved, but manufacturing precision deteriorates due to resist taper angle variations
Solution Approach 1:
The patent applies preliminary action by forming the buried diffusion area before forming the drift area. This sequence allows the buried diffusion area to be established at a controlled depth using low-energy ion implantation through a thick resist mask, before subsequent high-energy implantation forms the drift area. The preliminary formation of the buried diffusion area eliminates the need to control resist taper angles during high-energy implantation, thereby resolving the manufacturing precision issue while maintaining withstand voltage performance.
2Strength
If high-energy ion implantation is used to form buried diffusion areas, then withstand voltage increases, but device complexity increases due to need for precise control mechanisms
Solution Approach 1:
The patent eliminates complex control mechanisms by performing the buried diffusion area formation as a preliminary step before drift area formation. The low-energy ion implantation through a thick resist mask (5 μm or more) does not require precise taper angle control, simplifying the manufacturing process. The subsequent high-energy ion implantation for drift area formation also does not require buried diffusion area depth control, further reducing complexity.
Solution Approach 2:
The patent segments the ion implantation process into two distinct steps: first forming the buried diffusion area with low-energy implantation, then forming the drift area with high-energy implantation. This segmentation allows each step to use optimized implantation conditions independent of the other, eliminating the need for complex inter-step control mechanisms and simplifying the overall manufacturing process.
3Reliability
If drift area concentration is increased to reduce on-resistance, then on-resistance decreases, but withstand voltage deteriorates
Solution Approach 1:
The patent segments the semiconductor structure into distinct regions with different impurity concentrations: the buried diffusion area with high concentration for low on-resistance, and the drift area with controlled concentration for withstand voltage. This spatial segmentation allows each region to be optimized independently for its specific function, achieving both low on-resistance and high withstand voltage simultaneously.
Solution Approach 2:
The patent applies local quality by creating regions with different impurity concentrations at different locations. The buried diffusion area has high impurity concentration to reduce on-resistance, while the drift area has controlled lower concentration to maintain withstand voltage. This local differentiation of material properties allows simultaneous optimization of both on-resistance and withstand voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The proposed configuration achieves stable reduction in on-resistance and increase in withstand voltage without the need for epitaxial layers or precise resist taper angle control, enhancing manufacturing efficiency and cost-effectiveness.
Implementation Method 1
impurities of a different conductivity type from diffusion areas formed on the surface of a semiconductor substrate are diffused so as to form new diffusion areas
Implementation Method 2
the buried diffusion area 4 is formed through implantation under such conditions that the area is buried inside the drift area 5
Data Source
AI summary
Provided are a semiconductor device which can be manufactured at low cost and has a low on-resistance and a high withstand voltage, and its manufacturing method. The semiconductor device comprises an N-type well area formed on a P-type semiconductor substrate, a P-type body area formed within the well area, an N-type source area formed within the body area, an N-type drain area formed at a distance from the body area within the well area, a gate insulating film formed so as to overlay a part of the body area, a gate electrode formed on the gate insulating film and a P-type buried diffusion area which makes contact with the bottom of the body area and extends to an area beneath the drain area in a direction parallel to the surface of the semiconductor substrate within the well area.