LDMOS Transistor with Buried Diffusion for High Current Density
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Solution Overview
Problem
Integrated circuits face challenges in efficiently managing both low and high voltage operations on the same chip, leading to increased complexity and cost, particularly in driver chips that require high current at high voltages, where LDMOS transistors often occupy a large area.
Innovation Solution
The implementation of LDMOS transistors with multiple current channels, both above and below a buried p-type diffusion, allows for high current capability in a reduced area by enabling current to flow through multiple paths, thereby reducing the overall area and cost requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If LDMOS transistors are used to provide high current at high voltages, then the current capability is improved, but the chip area occupied increases significantly
Solution Approach 1:
The LDMOS transistor is divided into multiple parallel current channels (first current channel above buried p-type diffusion, second current channel below buried p-type diffusion). This segmentation allows the total current to be distributed across multiple paths, achieving high current capability while reducing the area required per channel.
Solution Approach 2:
The patent utilizes the vertical dimension by creating current channels both above and below the buried p-type diffusion layer. This three-dimensional current path arrangement allows current to flow through multiple spatial levels, increasing current density without proportionally increasing planar chip area.
2Adaptability or versatility
If multiple gate oxide thicknesses are used to support both low voltage and high voltage transistors, then voltage compatibility is improved, but process complexity increases
Solution Approach 1:
The LDMOS transistor structure creates localized high voltage handling capability through the lightly doped lateral diffused drain region and buried p-type diffusion, while other regions of the chip can maintain standard low voltage characteristics. This allows different voltage operations in different locations without requiring multiple gate oxide thicknesses across the entire chip.
Solution Approach 2:
The LDMOS transistor structure serves multiple functions: it provides high voltage switching capability, handles high current, and maintains compatibility with standard CMOS fabrication processes. This multi-functionality eliminates the need for separate process streams for low and high voltage devices.
3Power
If LDMOS transistors are designed for high voltage operation, then voltage handling capability is improved, but the peak electric field increases
Solution Approach 1:
The voltage drop across the LDMOS transistor is segmented across multiple depletion regions: the lightly doped lateral diffused drain region, the buried p-type diffusion, and the channel region. This segmentation distributes the electric field stress across multiple zones, reducing the peak electric field in any single region while maintaining high voltage capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design enables high current capability at high voltages with reduced area occupation, allowing for efficient use of the same low voltage gate dielectric and reducing the peak electric field, thus enabling higher diode breakdown voltage and smaller chip area usage.
Implementation Method 1
A depletion region forms in this lightly doped lateral diffused region resulting in a voltage drop between the drain contact and the transistor gate
Implementation Method 2
A depletion region forms in this lightly doped lateral diffused region resulting in a voltage drop between the drain contact and the transistor gate
Implementation Method 3
A first current channel may be above a buried p-type diffusion and a second current channel may be below the buried p-type diffusion
Data Source
AI summary
An integrated circuit and method having an LDMOS transistor with multiple current channels. A first current channel is above a buried p-type diffusion and a second one current channel is below the buried p-type diffusion.