LDMOS Buried-Layer Layout for High Breakdown Voltage
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Solution Overview
Problem
High voltage semiconductor devices, such as LDMOS transistors, face challenges in achieving a sufficient depletion layer and high breakdown voltage while maintaining a reduced size, as a thick P-type epitaxial layer can disrupt the bonding between the N-type deep well region and the N-type buried layer, affecting device functionality.
Innovation Solution
The semiconductor device incorporates a first conductive type buried layer with a second region that is in direct contact with the N-type deep well region, allowing for the formation of a second N-type buried layer between them, which enhances the depletion layer and breakdown voltage without increasing the device size, through a specific manufacturing process involving doping and thermal diffusion.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a thick P-type epitaxial layer is formed to achieve sufficient depletion layer and high breakdown voltage, then the breakdown voltage is improved, but the bonding between N-type deep well region and N-type buried layer is disrupted, affecting device functionality
Solution Approach 1:
The P-type buried layer is segmented into two distinct regions: a first region with higher resistivity and a second region with lower resistivity. This segmentation allows the first region to support high breakdown voltage while the second region ensures proper bonding with the N-type deep well region, resolving the contradiction between achieving high breakdown voltage and maintaining reliable bonding.
Solution Approach 2:
Different regions of the P-type buried layer are assigned different electrical properties (resistivity values). The first region has higher resistivity to enhance breakdown voltage, while the second region has lower resistivity to facilitate bonding. This local differentiation of properties allows simultaneous achievement of high breakdown voltage and reliable bonding functionality.
2Strength
If the P-type epitaxial layer thickness is increased to improve breakdown voltage, then the withstand voltage is improved, but the device size increases
Solution Approach 1:
Instead of increasing the physical thickness of the P-type epitaxial layer to improve breakdown voltage, the invention changes the electrical parameters (resistivity) of different regions within the buried layer. The first region has higher resistivity to enhance breakdown voltage, while the second region has lower resistivity for bonding, achieving high withstand voltage without increasing device size.
3Volume of moving object
If a typical RESURF structure with N-type deep well region bonded to N-type buried layer is used to reduce device size, then the device size is reduced, but the breakdown voltage may be insufficient without proper bonding
Solution Approach 1:
The P-type buried layer is divided into two regions with different resistivities. The first region provides the necessary electrical characteristics for high breakdown voltage in the RESURF structure, while the second region ensures proper bonding between the N-type deep well region and N-type buried layer, maintaining both compact size and high breakdown voltage performance.
Solution Approach 2:
Different regions of the buried layer are optimized for different functions: the first region with higher resistivity optimizes breakdown voltage for the RESURF effect, while the second region with lower resistivity optimizes bonding. This local quality differentiation enables the compact RESURF structure to achieve both high breakdown voltage and reliable bonding simultaneously.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables a high breakdown voltage and high integration density in a compact form factor, improving the performance and reliability of high voltage semiconductor devices.
Implementation Method 1
forming a first conductive type buried layer on the substrate... comprising: forming a first region by implanting a first conductive type impurity into a top surface of the substrate
Implementation Method 2
forming a second region by further implanting the first conductive type impurity into the first region... a top surface of the second region is disposed closer to a surface of the substrate than a top surface of the first region
Data Source
AI summary
A semiconductor device and a manufacturing method thereof are provided. The semiconductor device includes: a first conductive type buried layer disposed on a substrate; a first conductive type deep well region, a second conductive type body region, and a first conductive type drift region which are disposed on the first conductive type buried layer; a source region disposed in the second conductive type body region; a drain region disposed in the first conductive type deep well region; and a gate electrode disposed on the second conductive type body region and the first conductive type drift region.