LDMOS Device with Buried Layer for Breakdown Voltage
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Solution Overview
Problem
Conventional power MOSFETs, such as LDMOS, face limitations in achieving high breakdown voltage and low turn on resistance, which are crucial for efficient power switch functions.
Innovation Solution
The semiconductor device incorporates a gate on a substrate with a source and drain region, a body region, device isolation, and buried layers to create a balanced electric field, allowing for increased breakdown voltage and reduced turn on resistance through optimized doping concentrations and structural design.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional LDMOS structure is used, then device simplicity is maintained, but breakdown voltage is limited and turn on resistance cannot be sufficiently reduced
Solution Approach 1:
The device structure is segmented into multiple functional regions including a body region, a first well region, and a second well region with different conductive types. These segmented regions are arranged in specific spatial relationships to create balanced electric fields, thereby increasing breakdown voltage while maintaining manageable device complexity through systematic regional division
Solution Approach 2:
Different regions of the device are assigned different local qualities through selective doping: the body region has one conductive type while the well regions have opposite conductive types. This local quality differentiation creates optimized electric field distributions in specific areas, enabling higher breakdown voltage without uniformly increasing device complexity throughout the entire structure
2Reliability
If higher breakdown voltage is achieved through conventional means, then voltage handling improves, but turn on resistance increases
Solution Approach 1:
The invention changes key parameters including doping concentrations and spatial dimensions of different regions. By optimizing the doping concentrations in the body region and well regions, and by adjusting their relative positions and sizes, the device achieves a parameter set that simultaneously enables high breakdown voltage and low turn on resistance through balanced electric field characteristics
3Loss of energy
If device structure is optimized for low turn on resistance, then current flow improves, but breakdown voltage decreases
Solution Approach 1:
The device employs asymmetric structural design where the body region and well regions have different geometries, doping concentrations, and spatial arrangements. This asymmetry allows the electric field to be distributed differently in various regions, enabling the device to achieve both low turn on resistance through optimized current path regions and high breakdown voltage through field-balancing regions with opposite conductive types
Data Source
AI summary
A semiconductor device is provided. The semiconductor device includes a gate on a substrate, a source region at a first side of the gate, a first conductive type body region under the source region, a second conductive type drain region at a second side of the gate, a device isolation region in the substrate between the source region and the drain region and overlapping part of the gate, and a first buried layer extending in a direction from the source region to the drain region, the first buried layer under the body region, overlapping part of the device isolation region, and not overlapping the drain region.