LDMOS Breakdown Voltage via Buried Layer
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Solution Overview
Problem
Lateral-diffused-metal-oxide-semiconductor (LDMOS) devices often exhibit lower source-drain breakdown voltage (BVDSS) due to operational asymmetry, with the asymmetric region having significantly lower BVDSS compared to the symmetrical region, limiting overall device performance.
Innovation Solution
Incorporating a buried layer (BL) region of opposite conductivity type proximate to the deep trench isolation (DTI) region in the asymmetric LDMOS region, which raises the breakdown voltage to match that of the symmetrical region, thereby improving overall BVDSS.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If LDMOS device structure is used, then high power handling capability is achieved, but source-drain breakdown voltage is reduced due to operational asymmetry
Solution Approach 1:
The patent introduces a buried layer region with specific doping characteristics (opposite conductivity type, specific depth and concentration) localized in the asymmetric region near the DTI region. This local structural modification creates different electrical properties in different regions of the device, specifically enhancing the breakdown voltage in the asymmetric region without affecting the overall power handling capability of the LDMOS structure.
2Device complexity
If asymmetric region design is used, then device complexity is reduced, but breakdown voltage uniformity deteriorates
Solution Approach 1:
Rather than redesigning the entire device structure, the patent applies a localized buried layer region specifically in the asymmetric area. This maintains the overall simplicity of the LDMOS structure while locally correcting the breakdown voltage uniformity issue through targeted structural modification.
Solution Approach 2:
The patent addresses the two-dimensional asymmetry issue by introducing a vertical dimension element - the buried layer region extending from the surface into the substrate. This vertical structure modifies the electric field distribution in the asymmetric region, achieving breakdown voltage uniformity without complicating the planar device layout.
Data Source
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AI summary
A multi-region (81, 83) lateral-diffused-metal-oxide-semiconductor (LDMOS) device (40) has a semiconductor-on-insulator (SOI) support structure (21) on or over which are formed a substantially symmetrical, laterally internal, first LDMOS region (81) and a substantially asymmetric, laterally edge-proximate, second LDMOS region (83). A deep-trench isolation (DTI) wall (60) substantially laterally terminates the laterally edge-proximate second LDMOS region (83). Electric field enhancement and lower source-drain breakdown voltages (BVDSS) exhibited by the laterally edge-proximate second LDMOS region (83) associated with the DTI wall (60) are avoided by providing a doped SC buried layer region (86) in the SOI support structure (21) proximate the DTI wall (60), underlying a portion of the laterally edge-proximate second LDMOS region (83) and of opposite conductivity type than a drain region (31) of the laterally edge-proximate second LDMOS region (83).