LDMOS Buried Layer Alignment With STI for Breakdown Voltage
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Solution Overview
Problem
Lateral drain metal oxide semiconductor (LDMOS) devices in power management integrated circuits face challenges in achieving high breakdown voltage and low on-resistance, which are crucial for efficient power conversion and low power consumption.
Innovation Solution
The method involves forming a trench in a substrate, implanting dopants to create a buried layer and a drift implantation layer, and depositing a dielectric material, resulting in a device with a well region, body region, drift region, source region, drain region, and a gate structure, where the buried layer is aligned with the shallow trench isolation structure, optimizing doping concentrations and alignment to enhance breakdown voltage and reduce on-resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the LDMOS device uses conventional doping and structure design, then the manufacturing process is simple, but the breakdown voltage is low and on-resistance is high
Solution Approach 1:
The device is segmented into multiple functional regions with distinct doping profiles: a first doped region (highly doped, same type as drift region) positioned deeper in the substrate, and a second doped region (lightly doped, same type as drift region) positioned shallower. This segmentation allows the highly doped region to provide low on-resistance while the lightly doped region contributes to high breakdown voltage, resolving the contradiction between reliability and device complexity.
Solution Approach 2:
Different regions of the device are assigned different doping concentrations and types to optimize local functions. The first doped region has high doping concentration for low resistance contact, while the second doped region has low doping concentration for high breakdown voltage. The gate structure also has localized doping in the channel region. This local quality differentiation enables the device to simultaneously achieve high breakdown voltage and low on-resistance.
2Reliability
If the LDMOS device optimizes for high breakdown voltage through increased drift region length, then breakdown voltage improves, but on-resistance increases and device area expands
Solution Approach 1:
The invention introduces a vertical dimension solution by placing the first doped region at a greater depth than the second doped region in the substrate. This vertical stacking arrangement allows the highly doped first region to provide low resistance pathways without increasing the lateral drift region length, thus maintaining compact device area while achieving high breakdown voltage through the combined effect of both doped regions.
Solution Approach 2:
The device employs a composite doping structure combining two differently doped regions of the same conductivity type, along with a gate structure having specific doping characteristics. This composite approach creates a multi-functional doping profile where the first doped region provides low resistance and the second doped region provides high breakdown voltage, achieving both goals without increasing device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach increases the drain-to-source breakdown voltage while maintaining low specific on-resistance, ensuring effective power conversion and stability across varying fabrication conditions.
Implementation Method 1
implanting a first dopant having a first conductive type into the substrate in a direction perpendicular to a major surface of the substrate by utilizing edges of the trench as an implantation mask
Data Source
AI summary
A lateral drain metal oxide semiconductor (LDMOS) device includes a well region having a second conductive type in a substrate, a body region having a first conductive type in the well region, a drift region having the second conductive type in the well region and spaced apart from the body region, a source region having the second conductive type in the body region, a drain region having the second conductive type in the drift region, a gate structure on the well region between the source region and the drain region, a shallow trench isolation (STI) structure in the drift region between the drain region and the source region, and a buried layer having the first conductive type in the well region under the drift region, a center of the buried layer being aligned with a center of the STI structure.