LDMOS Transistor Breakdown Voltage via Buried Region Isolation
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Solution Overview
Problem
Existing LDMOS transistors face challenges in achieving high breakdown voltage due to early punch-through between the n-well region and p-type substrate, and the complexity of manufacturing processes, particularly in securing a high breakdown voltage without additional n-type regions on the back side.
Innovation Solution
A semiconductor device with a first insulated-gate field-effect transistor featuring a semiconductor substrate with a buried region of a first conductivity type, a body region of the same conductivity type, a source region of a second conductivity type, and an impurity region of the second conductivity type, where the impurity region isolates the buried and body regions, enhancing breakdown voltage and simplifying the manufacturing process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If an n-type body region is electrically coupled to the n-type buried region to form a back-gate structure, then the transistor can be fabricated, but the breakdown voltage in the depth direction between the drain and the n-type buried region cannot be increased because the potential of the n-type body region approximately equals the potential of the n-type buried region
Solution Approach 1:
The patent divides the n-type body region into two separate regions: an n-type body region and an n-type extension region. These two regions are electrically isolated from each other, allowing independent potential control. The n-type extension region can be maintained at a higher potential than the n-type body region, thereby increasing the breakdown voltage in the depth direction without requiring a complex back-gate structure.
Solution Approach 2:
The patent introduces a p-type impurity region as an intermediary between the n-type body region and the n-type extension region. This p-type impurity region electrically isolates the two n-type regions, enabling them to have different potentials while maintaining a simplified structure without additional back-gate components.
2Ease of manufacture
If no n-type buried region is included to simplify the structure, then manufacturing is simpler, but punching-through occurs early between the n-well region and the p-type substrate region, so that a high breakdown voltage cannot be secured
Solution Approach 1:
The patent segments the n-type body region into two electrically isolated parts (n-type body region and n-type extension region) separated by a p-type impurity region. This segmentation allows the n-type extension region to prevent early punch-through between the n-well region and p-type substrate region, securing high breakdown voltage while maintaining manufacturing simplicity.
3Reliability
If an n-type region is added on the back side to increase the breakdown voltage of the under-drain region, then the breakdown voltage is increased, but the manufacturing process becomes complicated
Solution Approach 1:
Instead of adding an n-type region on the back side (vertical dimension), the patent achieves the same effect by introducing a p-type impurity region within the substrate (horizontal dimension). This approach increases the breakdown voltage of the under-drain region by electrically isolating the n-type body region from the p-type substrate region, avoiding the need for additional back-side processing steps.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution effectively secures a high breakdown voltage while simplifying the manufacturing process by electrically isolating the buried and body regions, thereby improving the transistor's performance and manufacturing efficiency.
Implementation Method 1
A first impurity region of a second conductivity type is formed between the first buried region and the first body region, the first impurity region isolating the first buried region and the first body region from each other
Data Source
AI summary
A semiconductor device which can secure a high breakdown voltage and to which a simplified manufacturing process is applicable and a method for manufacturing the semiconductor device are provided. An n+ buried region has a floating potential. An n-type body region is located on a first surface side of the n+ buried region. A p+ source region is located in the first surface and forms a p-n junction with the n-type body region. A p+ drain region is located in the first surface spacedly from the p+ source region. A p-type impurity region PIR is located between the n+ buried region and the n-type body region and isolates the n+ buried region and the n-type body region from each other.