P-type LDMOS Fabrication for Uniform Channel Control
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Solution Overview
Problem
Conventional P-type LDMOS devices face challenges in achieving uniformity and stability due to issues like short channel effects, impurity diffusion, and high leakage currents, which are exacerbated by rapid thermal annealing and the use of tungsten/silicon bi-layers that lead to non-uniform threshold voltages and increased depletion.
Innovation Solution
A method for fabricating a P-type surface-channel LDMOS device with improved in-plane uniformity involves sequential steps including N-type epitaxial growth, controlled ion implantations, high-temperature drive-in processes, and careful deposition of silicon oxide and polysilicon layers to prevent boron penetration and diffusion, ensuring stable channel formation and gate structure integrity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If rapid thermal annealing process is used to form N-type channel, then threshold voltage can be reduced for high switching speed, but channel length becomes short and inter-process variation increases
Solution Approach 1:
The patent changes the thermal processing parameters by using a long-time high-temperature drive-in process (900-1050°C for 30-180 minutes) instead of rapid thermal annealing. This parameter change allows sufficient time for controlled ion diffusion to form the N-type channel, achieving desired channel length and uniformity while avoiding the short channel effects associated with rapid processing
Solution Approach 2:
The patent performs preliminary actions by forming the N-type channel and lightly doped drain drift regions through long-time high-temperature drive-in before subsequent processing steps. This preliminary formation ensures proper channel length and doping distribution is established before gate structure completion, preventing later adjustments that could compromise uniformity
2Manufacturing precision
If long-time high-temperature drive-in process is used instead of rapid thermal annealing, then channel length uniformity is improved, but impurity diffusion into channel and boron penetration through gate oxide increases
Solution Approach 1:
The patent performs preliminary formation of the N-type channel and lightly doped drain drift regions through long-time high-temperature drive-in before completing the gate structure with polysilicon gate and tungsten/silicon bi-layer. By establishing proper doping distribution beforehand, subsequent processing steps do not require additional high-temperature exposure that would cause harmful impurity diffusion or boron penetration
Solution Approach 2:
The patent uses the gate oxide layer as an intermediary barrier that protects the channel from boron penetration. The gate oxide is formed and maintained intact during processing, serving as a protective layer that prevents boron from the polysilicon gate and tungsten/silicon bi-layer from diffusing into the channel region during subsequent processing steps
3Ease of manufacture
If polysilicon gate with tungsten/silicon bi-layer is formed, then gate structure is completed, but boron diffuses into tungsten/silicon bi-layer causing threshold voltage non-uniformity and increased depletion
Solution Approach 1:
The patent performs preliminary formation of the N-type channel and lightly doped drain drift regions through long-time high-temperature drive-in before completing the gate structure. This sequencing ensures that critical doping patterns are established before any subsequent gate processing, preventing boron diffusion into the tungsten/silicon bi-layer that would occur if gate structure formation preceded channel formation
Solution Approach 2:
The patent converts the potential harm of boron diffusion into a benefit by using the gate oxide layer as a protective barrier. The gate oxide, which would normally be a site for boron accumulation, is instead used as a diffusion barrier that protects the channel from boron penetration while allowing the gate structure to be completed with standard polysilicon and tungsten/silicon bi-layer materials
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a device with enhanced uniformity and stability, preventing depletion and leakage, and allowing for a desired channel length, thereby improving the overall performance and reliability of the P-type LDMOS device.
Implementation Method 1
growing an N-type epitaxial layer 2 over the heavily doped N-type substrate 1
Implementation Method 2
performing a first P-type ion implantation to form the first lightly doped drain drift diffusion region 6
Implementation Method 3
performing an N-type channel ion implantation process and a rapid thermal annealing process to form the N-type channel 5
Implementation Method 4
performing a first P-type ion implantation, followed by a high-temperature drive-in process, thereby forming a first lightly doped drain drift diffusion region
Data Source
AI summary
A method of fabricating a P-type surface-channel laterally diffused metal oxide semiconductor device includes forming a gate structure with polysilicon and metal silicide, and the processes of channel implantation, long-time high-temperature drive-in, formation of a heavily doped N-type polysilicon sinker and boron doping of a polysilicon gate, are performed in this order, thereby ensuring the gate not to be doped with boron during its formation. The high-temperature drive-in process is allowed to be carried out to form a channel with a desired width, and a short channel effect which may cause penetration or electric leakage of the resulting device is prevented. As the polysilicon gate is not processed by any high-temperature drive-in process after it is doped with boron, the penetration of boron through a gate oxide layer and the diffusion of N-type impurity contained in the heavily doped polysilicon sinker into the channel or other regions are prevented.