LDMOS Transistor Channel Length Variation Reduction
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Solution Overview
Problem
Conventional LDMOS transistors experience run-to-run variation in channel length due to mask alignment errors, leading to inconsistent breakdown voltage and on-resistance.
Innovation Solution
A method for fabricating MOS transistors with a self-aligned extension region, defined by a self-aligned lightly doped region and a self-aligned extension region, which reduces channel length variation and aligns with the gate, thereby stabilizing the channel length and improving transistor performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a mask is used to form the second well in a conventional LDMOS transistor, then the well can be formed with proper positioning, but mask alignment error causes channel length variation from run to run
Solution Approach 1:
The patent applies self-alignment techniques where the extension region is formed using the gate structure as a reference, eliminating the need for separate mask alignment steps. The source region is self-aligned to the gate, and the extension region is defined by a self-aligned lightly doped region, allowing the structure to define its own positions without external masking, thus eliminating mask alignment errors that cause run-to-run variation in channel length and resulting breakdown voltage and on-resistance
Solution Approach 2:
The patent forms the self-aligned lightly doped region and extension region in advance of the final channel definition step. By pre-defining these regions with proper alignment to the gate structure before subsequent processing steps, the channel length is predetermined with high precision, preventing variation in final device characteristics
2Reliability
If the channel length is precisely controlled, then breakdown voltage and on-resistance can be optimized, but conventional fabrication methods cannot achieve consistent channel length across runs
Solution Approach 1:
The self-aligned fabrication methodology uses the gate structure and previously formed regions as references to automatically define subsequent feature positions. The extension region aligns itself to the gate without requiring additional mask alignment, ensuring that channel length is consistently defined by the physical structures already in place rather than by variable mask positioning, thereby achieving run-to-run consistency in breakdown voltage and on-resistance
Data Source
AI summary
According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a self-aligned lightly doped region in a first well underlying a first sidewall of a gate. The method further includes forming a self-aligned extension region under a second sidewall of the gate, where the self-aligned extension region extends into the first well from a second well. The method further includes forming a drain region spaced apart from the second sidewall of the gate. The method further includes forming a source region in the self-aligned lightly doped region and the first well. The self-aligned lightly doped region and the self-aligned extension region define a channel length of the MOS transistor, such as an LDMOS transistor.