LDMOS Channel Region Segmentation for Patterning Tolerance
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Solution Overview
Problem
The existing LDMOSFET manufacturing techniques face challenges in minimizing the channel region area and improving performance due to variations in masking and exposure accuracy, leading to increased on-resistance and decreased off-breakdown voltage, particularly when neighboring LDMOSs share a p-type well region.
Innovation Solution
A semiconductor device and method where a first channel region with a lower impurity concentration than the first channel region is formed, partially overlapping a first gate electrode, with the end of the well region positioned at a distance from the gate electrode to reduce channel length variability and enhance performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If the gate electrode end is positioned at a sufficient distance from the p-type well region end to account for patterning variation, then the channel length is determined, but the channel region length becomes larger than required, increasing device area
Solution Approach 1:
The patent divides the channel region into two distinct parts: a first channel region formed by ion implantation that extends beyond the gate electrode, and a second channel region formed by epitaxial growth that is self-aligned to the gate electrode. This segmentation allows the first channel region to provide buffer space for patterning variation while the second channel region provides the precise, controlled channel length needed for device performance, thereby reducing the total channel region area while maintaining manufacturing precision.
Solution Approach 2:
The patent introduces a vertical dimension by forming the first channel region through ion implantation at a deeper level and then forming the second channel region through epitaxial growth that is self-aligned to the gate electrode. This dimensional approach allows the channel regions to be stacked vertically with different horizontal extents, enabling the first channel region to extend beyond the gate for manufacturing tolerance while the second channel region provides the precise channel length, thus reducing the overall area.
2Area of stationary object
If the channel region length is reduced for miniaturization, then device area decreases, but on-resistance increases and off-breakdown voltage decreases
Solution Approach 1:
The patent applies local quality by creating two channel regions with different impurity concentrations and spatial distributions. The first channel region has a higher impurity concentration from ion implantation and extends beyond the gate electrode to provide low-resistance current paths, while the second channel region has a lower impurity concentration and is precisely aligned to the gate electrode to provide the required breakdown voltage. This local differentiation allows simultaneous optimization of on-resistance and off-breakdown voltage in different spatial zones.
Solution Approach 2:
The patent changes the impurity concentration parameter between the two channel regions. The first channel region is formed with higher impurity concentration through ion implantation to reduce on-resistance, while the second channel region is formed with lower impurity concentration through epitaxial growth to maintain off-breakdown voltage. This parameter variation allows the device to achieve both low on-resistance and high off-breakdown voltage despite reduced channel region area.
3Area of stationary object
If neighboring LDMOSs share a p-type well region to reduce area, then device density increases, but channel length control becomes more sensitive to patterning variation
Solution Approach 1:
The patent performs preliminary action by forming the first channel region through ion implantation before forming the gate electrode and before forming the second channel region. This first channel region extends beyond the gate electrode and serves as a pre-formed structure that provides buffer space for subsequent patterning variations. When the second channel region is formed by epitaxial growth self-aligned to the gate electrode, the preliminary first channel region ensures that even with patterning variation, the channel length control remains robust, enabling neighboring LDMOSs to share well regions effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a smaller channel region length, reducing on-resistance and maintaining or improving off-breakdown voltage, thereby enhancing the performance and miniaturization of LDMOSFETs.
Implementation Method 1
a first channel region and a first well region having a lower impurity concentration than the first channel region which are formed in a semiconductor substrate
Data Source
AI summary
A semiconductor device with improved performance. A channel region and a well region having a lower impurity concentration than the channel region are formed in a semiconductor substrate on the source region side of an LDMOS. The channel region partially overlaps a gate electrode in plan view. In the gate length direction of the LDMOS, an end of the well region in the channel region is at a distance from the end of the gate electrode on the source region side of the LDMOS in a manner to be away from the gate electrode.