LDMOS IC Chip A/L Ratio Integration
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Solution Overview
Problem
Current semiconductor processes are limited in producing IC chips with multiple voltage ratings and device types, such as switch and analog LDMOS devices, on a single chip, leading to increased chip size and production costs due to the need for separate ICs for each voltage rating and device type.
Innovation Solution
The integration of multiple LDMOS devices with different voltage ratings on a single substrate using a single process, where the A/L value of the isolation structure and gate conductive layer length are adjusted to differentiate between switch and analog devices, allowing for concurrent fabrication of devices with varying characteristics.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If multiple LDMOS devices with different voltage ratings are fabricated using a single process on one chip, then chip area utilization improves and production cost decreases, but device performance precision and characteristic differentiation deteriorate
Solution Approach 1:
The patent applies local quality by configuring different A/L ratios in different regions of the same chip. Specifically, the first LDMOS device has a first A/L ratio optimized for switch device performance, while the second LDMOS device has a second A/L ratio optimized for analog device performance. This allows each region to have locally optimized characteristics despite being fabricated in a single process, thereby resolving the contradiction between chip area utilization and device performance precision.
2Reliability
If separate IC chips are used for different voltage ratings and device types, then device performance and characteristics are optimized, but chip size and production cost increase
Solution Approach 1:
The patent merges multiple LDMOS devices with different voltage ratings and device types (switch and analog) onto a single chip. By configuring different A/L ratios for different devices on the same chip, the patent achieves both device characteristic optimization and system simplification, effectively resolving the contradiction between reliability and device complexity.
Solution Approach 2:
The patent creates a universal chip platform that can accommodate multiple types of LDMOS devices (switch and analog) with different voltage ratings. The isolation structure and configurable A/L ratios enable the single chip to perform multiple functions that previously required separate dedicated chips, thereby reducing system complexity while maintaining device performance.
3Adaptability or versatility
If the isolation structure length A and gate conductive layer length L are adjusted to differentiate device characteristics, then device versatility improves, but manufacturing process complexity increases
Solution Approach 1:
The patent utilizes parameter changes by adjusting the A/L ratio to differentiate device characteristics. By varying the isolation structure length A and/or gate conductive layer length L, the patent can optimize devices for different applications (switch vs. analog) without changing the fundamental fabrication process. This approach improves device versatility while keeping manufacturing process complexity manageable.
Data Source
AI summary
An IC chip, including a switch LDMOS device and an analog LDMOS device, is configured on a substrate having a first conductive type. Components of the two LDMOS devices respectively include two gate conductive layers configured on two first active regions of the substrate. A common source contact region having a second conductive type is configured in a second active region, which is configured between the two first active regions. An isolation structure is included for isolating the second active region and the first active regions. The isolation structure between the first active regions and the second active region has a length “A” extending along a longitudinal direction of a channel under each gate conductive layer, and each gate conductive layer on each first active region has a length “L” extending along the longitudinal direction of the channel, the two LDMOS devices have different A/L values.