LDMOS with corrugated drift region for breakdown voltage
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Solution Overview
Problem
LDMOS devices face a trade-off between high breakdown voltage and low on-state resistance, where increasing the drift area length to enhance breakdown voltage also increases on-state resistance, which is undesirable.
Innovation Solution
The introduction of trench regions within the extended drain region of LDMOS devices, which increase resistivity and allow for a shorter drift region length while maintaining or improving breakdown voltage, achieved through the use of multiple trench regions and varying depths and filler materials to optimize device layout and electric field manipulation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drift area length is increased to enhance breakdown voltage, then breakdown voltage is improved, but on-state resistance increases which is undesirable
Solution Approach 1:
The drift region is segmented into multiple sections by introducing trench regions that divide the extended drain region into separate zones. This segmentation allows the drift region to be divided into multiple shorter segments, each contributing to breakdown voltage while reducing the overall on-state resistance by preventing the cumulative resistance effect of a single long drift region.
Solution Approach 2:
Different regions of the drift area are given different properties through the introduction of trenches with varying depths, spacing, and filler materials. The drift region is divided into zones with different resistivity characteristics, allowing optimal local control of electric field distribution and carrier transport, thereby achieving high breakdown voltage without excessive on-state resistance.
2Object-affected harmful factors
If trench regions are introduced to reduce drift region length, then on-state resistance is reduced, but device complexity increases
Solution Approach 1:
The trench regions extend vertically into the drift region, utilizing the depth dimension to achieve field control without increasing lateral footprint. By introducing vertical structures (trenches) into the horizontally-oriented drift region, the patent achieves compactness in the plane while managing electric fields through the third dimension, thus reducing on-state resistance without proportionally increasing overall device complexity.
Solution Approach 2:
The trenches are configured with variable parameters including different depths, spacing distances, and filler material properties. By optimizing these parameters, the patent achieves effective field control and resistance reduction while maintaining manufacturability. The parameter optimization allows standard fabrication processes to be used, mitigating the increase in device complexity.
Data Source
AI summary
Semiconductor devices, such as LDMOS devices, are described that include a plurality of trench regions formed in an extended drain region of the devices. In one or more implementations, the semiconductor devices include a substrate having an extended drain region, a source region, and a drain region, all of the first conductivity type, formed proximate to a surface of the substrate. A gate is positioned over the surface and between the source region and the drain region. The gate is configured to receive a voltage so that a conduction region may be formed at least partially below the gate to allow charge carriers (e.g., majority carriers) to travel between the source region and the drain region. A plurality of trench regions are formed within the extended drain region that are configured to increase resistivity within the extended drain region when charge carriers travel between the source region and the drain region.