LDMOS Deep Trench Isolation for Breakdown Voltage

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Solution Overview

Problem

Conventional lateral diffused metal oxide semiconductor transistors (LDMOS) face challenges in miniaturization due to increased device size from field oxide and well isolation methods, which hinder breakdown voltage enhancement and device pitch reduction.

Innovation Solution

The implementation of a deep trench isolation structure adjacent to or surrounding the n-type well region in LDMOS devices, filled with dielectric material, to insulate junction breakdown paths and enhance breakdown voltage without increasing process steps or cost.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If field oxide layers and well regions are extended to increase isolation between devices, then isolation effectiveness is improved, but device size increases

Engineering Contradiction:
Improveisolation effectivenessVSAvoiddevice size
Core Design Contradiction:
ReliabilityVSArea of stationary object

Solution Approach 1:

The patent transitions from planar isolation methods (field oxide layers on the surface) to vertical isolation (deep trench isolation structures extending into the substrate). By adding the depth dimension, the isolation effectiveness is enhanced without proportionally increasing the lateral device footprint, thus resolving the contradiction between isolation quality and device size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The deep trench isolation structures are nested within or adjacent to the existing device structure, integrating the isolation function into the overall device architecture. This nested approach allows effective isolation to be achieved within the confined device area, preventing the need for extended field oxide regions.

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If device size is reduced for miniaturization, then integration density is improved, but breakdown voltage decreases due to insufficient isolation

Engineering Contradiction:
Improvedevice sizeVSAvoidbreakdown voltage
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

By implementing deep trench isolation that extends vertically into the substrate, the patent achieves effective electrical isolation in the depth dimension. This allows miniaturized lateral dimensions while maintaining adequate isolation performance, thereby preserving breakdown voltage characteristics despite reduced device size.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The deep trench isolation structures are strategically positioned at critical locations where breakdown paths occur, providing localized enhancement of isolation effectiveness. This targeted approach ensures breakdown voltage is maintained in critical regions without requiring uniform increase in overall device dimensions.

Inventive Principle:
Principle #3Local quality

3Ease of manufacture

If conventional isolation methods are used, then manufacturing process is simple, but device pitch cannot be reduced

Engineering Contradiction:
Improveprocess simplicityVSAvoiddevice pitch
Core Design Contradiction:
Ease of manufactureVSLength of moving object

Solution Approach 1:

The deep trench isolation utilizes the vertical dimension for isolation, which allows for reduced lateral spacing between devices. The trench structures can be formed using standard semiconductor fabrication processes, maintaining manufacturing simplicity while enabling smaller device pitch through improved vertical confinement of electrical fields.

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively increases breakdown voltage and reduces device size by isolating weak points in the n-type well region, improving voltage resistance and device integrity while allowing for further miniaturization without additional processing costs.

Implementation Method 1

A deep trench isolation structure is formed at an interface between the n-type well region and the p-type bulk for insulating a junction breakdown path between the n-type well region and the p-type bulk

Methodology Applied
Scientific EffectElectrical insulation: Electrical Resistance

Data Source

PatentUS20100270615A1Method for increasing breaking down voltage of lateral diffused metal oxide semiconductor transistor
Publication Date: 2010.10.28 VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
  • US20100270615A1 patent drawing
  • US20100270615A1 patent drawing
  • US20100270615A1 patent drawing

AI summary

A lateral diffused metal oxide semiconductor transistor is disclosed. A p-type bulk is disposed on a substrate. An n-type well region is disposed in the p-type bulk. A plurality of field oxide layers are disposed on the p-type bulk and the n-type well region. A gate structure is disposed on a portion of the p-type bulk and one of the plurality of field oxide layers. At least one deep trench isolation structure is disposed in the p-type bulk and adjacent to the n-type well region.