LDMOS Deep Well Segmentation for High Breakdown Voltage

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Solution Overview

Problem

Conventional N-type LDMOS devices have a breakdown voltage limited to below 20 V, and existing methods to increase this voltage, such as forming deep wells or buried layers, are costly and not applicable to all applications, and fail to achieve a breakdown voltage of 100 V or more.

Innovation Solution

A method of fabricating a semiconductor device involving the formation of deep wells with different depths and dopant concentrations, along with buried layers, to increase the breakdown voltage between the drain and source regions, without requiring additional epitaxial or buried layers, by creating a high impedance path and optimizing the electric field distribution.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional methods (deep well or buried layer) are used to increase breakdown voltage, then breakdown voltage is improved, but manufacturing cost and device complexity increase

Engineering Contradiction:
Improvebreakdown voltageVSAvoidfabrication complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The deep well is segmented into multiple regions with different depths: a first deep well region extending deeper under the drain region, and a second deep well region extending shallower under the source region. This segmentation allows optimized electric field distribution without requiring additional epitaxial or buried layers, achieving high breakdown voltage with simplified fabrication

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

Different regions of the deep well are assigned different depths and dopant concentrations tailored to local requirements: the first deep well region under the drain has higher dopant concentration and greater depth for voltage blocking, while the second deep well region under the source has lower dopant concentration and shallower depth for field optimization, eliminating the need for complex buried layer structures

Inventive Principle:
Principle #3Local quality

2Reliability

If thick epitaxial layer and buried layer are formed to achieve high breakdown voltage, then breakdown voltage is improved, but manufacturing cost increases

Engineering Contradiction:
Improvebreakdown voltageVSAvoidfabrication cost
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The invention extracts and eliminates the need for additional thick epitaxial layers and buried layers from the conventional structure. By forming the deep well directly in the substrate with varying depths and dopant concentrations, the patent achieves high breakdown voltage without these extra components, significantly reducing manufacturing cost and process complexity

Inventive Principle:
Principle #2Taking out (Extraction)

Solution Approach 2:

The patent changes the parameters of the deep well structure by varying dopant concentration and well depth across different regions. The first deep well region has higher dopant concentration and greater depth, while the second deep well region has lower dopant concentration and shallower depth. This parameter variation achieves optimal electric field distribution and high breakdown voltage without requiring additional epitaxial or buried layers

Inventive Principle:
Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The method achieves a breakdown voltage of at least 700 V, effectively addressing the limitations of existing technologies while reducing fabrication costs and ensuring the device can withstand higher voltages without additional complex configurations.

Implementation Method 1

implanting ions into the substrate through the deep well mask pattern to form the deep well

Methodology Applied
Scientific EffectIon implantation: Ion Implantation

Data Source

PatentUS9245997B2Method of fabricating a LDMOS device having a first well depth less than a second well depth
Publication Date: 2016.01.26 SK KEYFOUNDRY INC
  • US9245997B2 patent drawing
  • US9245997B2 patent drawing
  • US9245997B2 patent drawing

AI summary

A method of fabricating a semiconductor device capable of increasing a breakdown voltage without an additional epitaxial layer or buried layer with respect to a high-voltage horizontal MOSFET.