LDMOS Gate Dielectric Extension for Breakdown Voltage Tuning
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Solution Overview
Problem
Existing LDMOS designs are constrained by manufacturer-specific design rules, limiting the ability to fine-tune parameters such as the gate dielectric layer length, which affects breakdown voltage and on-resistance, hindering customization for customer-specific requirements.
Innovation Solution
An LDMOS design with an adjustable length of the second gate dielectric layer, allowing for customization of breakdown voltage by adjusting the second length (L2) independently of manufacturer-defined dimensions, and optionally using a polysilicon layer or silicide block layer to enhance breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If the gate dielectric layer length is fixed according to manufacturer design rules, then manufacturing compliance is ensured, but customization capability for breakdown voltage adjustment is lost
Solution Approach 1:
The gate dielectric layer is divided into two separate layers: a first gate dielectric layer and a second gate dielectric layer. The first layer has a fixed length complying with manufacturer design rules, while the second layer has an adjustable length that extends toward the drain. This segmentation allows the device to meet manufacturing requirements while enabling customization of breakdown voltage through adjustment of the second layer's length.
Solution Approach 2:
The solution adds an additional dimensional element by introducing a second gate dielectric layer that extends in the horizontal direction toward the drain. This additional layer provides a new degree of freedom for adjusting breakdown voltage without affecting the vertical stack structure or the fixed dimensions required by design rules.
2Reliability
If the gate dielectric layer length is extended to adjust breakdown voltage, then customization is enabled, but manufacturing compliance with design rules may be violated
Solution Approach 1:
By segmenting the gate dielectric layer into two distinct layers with different functions, the invention allows the first layer to maintain fixed dimensions for design rule compliance while the second layer provides adjustable length for breakdown voltage control. This segmentation enables simultaneous satisfaction of manufacturing requirements and performance customization.
Solution Approach 2:
The first gate dielectric layer maintains uniform thickness and fixed length to comply with design rules, while the second gate dielectric layer has variable length extending toward the drain to locally adjust the electric field distribution and control breakdown voltage. Each layer has optimized local properties for its specific function.
Data Source
AI summary
An LDMOS includes a substrate. A gate electrode is disposed on the substrate. A first gate dielectric layer is disposed between the gate electrode and the substrate. A second gate dielectric layer includes a first part and a second part. A source is embedded in the substrate at one side of the gate electrode. A drain is embedded in the substrate at the other side of the gate electrode. The second part of the second gate dielectric layer is extended toward the drain along a horizontal direction. The first part is covered by the gate electrode, and the second part is not covered by the gate electrode. Along the horizontal direction, the first part has a first length, and the second part has a second length. The second length is adjustable for adjusting a breakdown voltage of the LDMOS.