LDMOS Transistor Doped Layer for Breakdown Voltage and ON-Resistance Trade-off
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Solution Overview
Problem
Conventional LDMOS transistor devices face a trade-off between achieving high breakdown voltage (BVD) and low ON-resistance (RON), with existing designs struggling to concurrently optimize both parameters.
Innovation Solution
The design incorporates a doped layer with a width larger than the base region, formed under the base region, which reduces the electrical field, allowing for a higher BVD and lower RON by adjusting the energy and dosage for forming the doped layer differently than the base region, and ensuring the doped layer's width is greater than the base region's width.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the drift region is designed with low dopant concentration and large area to achieve high breakdown voltage, then the breakdown voltage is improved, but the ON-resistance increases
Solution Approach 1:
The patent applies local quality by creating a doped layer with higher dopant concentration specifically in the drift region where it is needed most. This localized doping approach allows the drift region to maintain high breakdown voltage capability in the bulk while having reduced ON-resistance at critical locations, thereby resolving the trade-off between these two parameters.
Solution Approach 2:
The patent changes the dopant concentration parameter locally within the drift region by forming a doped layer with higher dopant concentration. This parameter change allows the structure to achieve both high breakdown voltage (through the overall low-doped drift region) and low ON-resistance (through the localized high-doped layer), effectively resolving the contradiction between these two parameters.
2Reliability
If the doped layer width is increased to reduce electrical field and improve breakdown voltage, then the breakdown voltage is improved, but the device area increases
Solution Approach 1:
The patent applies local quality by forming a doped layer that is localized within the drift region rather than extending across the entire device. This localized approach allows the doped layer to effectively reduce the electrical field and improve breakdown voltage without requiring a proportional increase in the overall device area, thus resolving the contradiction between breakdown voltage and device area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively lowers the RON/BVD ratio from 0.68 to 0.44, achieving a balance between high breakdown voltage and low ON-resistance.
Implementation Method 1
a doped layer formed under the base region... the doped layer is formed to reduce electrical field of the LDMOS transistor device
Data Source
AI summary
A LDMOS transistor device includes a substrate including a first insulating structure formed therein, a gate formed on the substrate and covering a portion of the first insulating structure, a drain region and a source region formed in the substrate at two respective sides of the gate, a base region encompassing the source region, and a doped layer formed under the base region. The drain region and the source region include a first conductivity type, the base region and the doped layer include a second conductivity type, and the second conductivity type is complementary to the first conductivity type. A top of the doped layer contacts a bottom of the base region. A width of the doped layer is larger than a width of the base region.