LDMOS Double Gate Oxide Structure for Voltage Compatibility
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Solution Overview
Problem
The integration of high voltage transistors with low voltage circuits in semiconductor devices often requires a level shifter, leading to increased chip size and signal delay due to the excessive generation of electrical fields at the drain side, which degrades device performance.
Innovation Solution
A semiconductor device with a lateral diffused metal oxide semiconductor (LDMOS) structure featuring a double gate oxide structure, where the second gate oxide adjacent to the drain is thicker than the first gate oxide, preventing excessive electrical field generation without the need for a level shifter, thereby reducing chip size and maintaining high voltage performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a level shifter is used to interface high voltage and low voltage circuits, then voltage compatibility is improved, but chip size increases and signal delay occurs
Solution Approach 1:
The patent extracts the level shifter component from the system by enabling the LDMOS device to directly interface with low voltage circuits through the asymmetric gate oxide structure, eliminating the need for separate level shifting circuitry and reducing chip area
Solution Approach 2:
The LDMOS device achieves multi-functionality by being able to operate in both high voltage mode (with full high voltage capability) and low voltage mode (directly interfacing with 3.3V or lower circuits), replacing what would traditionally require separate high voltage and low voltage circuit blocks with level shifters
2Adaptability or versatility
If a level shifter is used to interface high voltage and low voltage circuits, then voltage compatibility is improved, but signal delay increases
Solution Approach 1:
The patent removes the level shifter component from the signal path, eliminating the additional propagation delay that would occur through level shifting circuitry. The asymmetric gate oxide structure enables direct voltage interfacing without intermediate conversion stages
Solution Approach 2:
The asymmetric gate oxide structure is pre-configured during manufacturing with the thicker oxide region positioned to provide inherent voltage protection, eliminating the need for dynamic level shifting operations during circuit operation and reducing signal path complexity
3Reliability
If a thicker gate oxide is used at the drain side to prevent electrical field breakdown, then device reliability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent applies local quality by creating an asymmetric gate oxide structure where the oxide thickness varies spatially - thicker at the drain side to prevent breakdown and thinner at the source side for better performance - rather than using uniform thickness throughout, thus achieving enhanced reliability without requiring multiple separate gate oxide layers
Solution Approach 2:
The patent changes the physical parameter of gate oxide thickness from a uniform value to a spatially varying value, with the thickness parameter being larger at the drain region and smaller at the source region, optimizing both reliability and performance through parameter optimization rather than structural complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The double gate oxide structure effectively inhibits excessive electrical field generation at the drain side, allowing for low voltage operation without a level shifter, reducing chip size and enhancing manufacturing ease while maintaining high voltage performance.
Implementation Method 1
the second gate oxide adjacent to the drain is thicker than the first gate oxide, preventing excessive electrical field generation
Data Source
AI summary
Disclosed are a semiconductor device and a method of manufacturing the same. The semiconductor device includes a substrate formed therein with a first conductive type well, and an LDMOS device formed on the substrate. The LDMOS device includes a gate electrode, gate oxides formed below the gate electrode, a source region formed in the substrate at one side of the gate electrode, and a drain region formed in the substrate at an opposite side of the gate electrode. The gate oxide includes first and second gate oxides disposed side-by-side and having thicknesses different from each other.