LDMOS Double LDD Structure Reduces On-Resistance
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Solution Overview
Problem
Existing LDMOS transistors face challenges in achieving a balance between low on-resistance and high breakdown voltage due to high parasitic resistance and the triggering of parasitic bipolar devices, which results in significant conduction losses and device destruction.
Innovation Solution
The implementation of a double LDD (Lightly Doped Drain) structure with a higher doping concentration LDD-N1 region and a lower energy LDD-N2 region, along with a P+ implantation for avalanche improvement and a non-Gaussian doping profile, reduces on-resistance and maintains high breakdown voltage without increasing fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If a lightly doped LDD region is formed to increase breakdown voltage, then breakdown voltage is improved, but on-resistance increases due to low doping concentration
Solution Approach 1:
The LDD region is segmented into two distinct zones: an inner LDD-N1 region with higher doping concentration (1E16 to 1E18 atoms/cm³) and an outer LDD-N2 region with lower doping concentration (1E15 to 1E17 atoms/cm³). This segmentation allows the inner region to provide low resistance current paths while the outer region maintains high breakdown voltage, resolving the contradiction between low on-resistance and high breakdown voltage.
Solution Approach 2:
Different doping concentrations are applied to different spatial locations within the LDD region. The inner LDD-N1 region uses higher doping concentration to reduce local resistance, while the outer LDD-N2 region uses lower doping concentration to enhance breakdown voltage. This local quality differentiation optimizes both electrical conductivity and voltage breakdown characteristics simultaneously.
2Device complexity
If a single LDD structure is used to reduce fabrication complexity, then manufacturing is simplified, but parasitic resistance increases causing high on-resistance
Solution Approach 1:
The LDD structure is divided into two implantation regions (LDD-N1 and LDD-N2) with different doping concentrations and implantation energies. This segmentation reduces parasitic resistance by providing optimized current paths without significantly increasing fabrication complexity, as both regions are formed using sequential ion implantation processes.
3Reliability
If high doping concentration is used in drain region to reduce on-resistance, then on-resistance is reduced, but breakdown voltage decreases
Solution Approach 1:
High doping concentration (1E16 to 1E18 atoms/cm³) is applied locally in the inner LDD-N1 region to reduce on-resistance, while lower doping concentration (1E15 to 1E17 atoms/cm³) is applied in the outer LDD-N2 region to maintain high breakdown voltage. This spatial differentiation of doping quality resolves the contradiction between low on-resistance and high breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces on-resistance by 41% and Figure of Merit (FOM) by 61% compared to single LDD structures, while maintaining high breakdown voltage and reducing parasitic bipolar base resistance, thus optimizing device performance.
Implementation Method 1
after the formation of the LDD-N1 region, another LDD implantation with a higher doping concentration and lower energy is carried out above said LDD-N1 region with the same mask to form an LDD-N2 region
Data Source
AI summary
A LDMOS with double LDD and trenched drain is disclosed. According to some preferred embodiment of the present invention, the structure contains a double LDD region, including a high energy implantation to form lightly doped region and a low energy implantation thereon to provide a low resistance path for current flow without degrading breakdown voltage. At the same time, a P+ junction made by source mask is provided underneath source region to avoid latch-up effect from happening.