LDMOS Transistor Drain Drift Region Optimization
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Solution Overview
Problem
Current high-voltage LDMOS transistors face challenges in reducing the Rds*Cgd figure of merit, which is essential for high current and high frequency applications, due to difficulties in fabricating split or step gates and the resulting increased Rds values that limit high-speed mobile applications.
Innovation Solution
The implementation of a p-type substrate with a p-buried layer, n-type source and drain regions, and a gate electrode positioned between the source and drain, along with a drain drift region that includes multiple dopant concentration peaks to reduce both drain-to-source resistance (Rds) and gate-to-drain capacitance (Cgd) by optimizing the dopant concentration profiles and structure.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Object-affected harmful factors
If split or step gates are used to reduce Cgd, then gate-to-drain capacitance is reduced, but manufacturing complexity and cost increase
Solution Approach 1:
The patent modifies the dopant concentration parameters within the drain drift region to optimize the electrical characteristics. By creating specific dopant concentration profiles (including peaks and valleys) in the drain drift region, the invention achieves reduced Cgd and Rds without requiring complex split or step gate structures.
Solution Approach 2:
The patent applies local quality by creating regions with different dopant concentrations at specific locations within the drain drift region. The dopant concentration is varied locally to achieve optimal electrical performance in different areas, particularly near the gate and drain junctions, without changing the overall gate structure complexity.
2Object-affected harmful factors
If drain drift region is extended to reduce Cgd, then gate-to-drain capacitance is reduced, but device size increases
Solution Approach 1:
The patent achieves Cgd reduction through parameter optimization rather than dimensional extension. By modifying dopant concentration profiles, peak positions, and gradient characteristics within a compact drain drift region, the invention reduces Cgd without increasing device footprint.
Solution Approach 2:
The patent applies local quality by concentrating dopant variations in specific regions of the drain drift region that have the most impact on Cgd. This localized optimization allows effective capacitance reduction without extending the overall device dimensions.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces both Rds and Cgd values, improving the Rds*Cgd figure of merit, enhancing the transistor's performance in high current and high frequency applications while maintaining a reduced device size.
Implementation Method 1
the drain drift region reduces the magnitude of the drain-to-source electric field
Implementation Method 2
it is desirable to reduce the Rds value
Implementation Method 3
a gate that lies over and is isolated from the channel region by a gate dielectric layer
Data Source
AI summary
The Rds*Cgd figure of merit (FOM) of a laterally diffused metal oxide semiconductor (LDMOS) transistor is improved by forming the drain drift region with a number of dopant implants at a number of depths, and forming a step-shaped back gate region with a number of dopant implants at a number of depths to adjoin the drain drift region.