LDMOS Drift Region Structure for High Breakdown in Standard CMOS
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Solution Overview
Problem
Conventional high-voltage transistors require large IC area, specialized processing, and exotic materials, making them costly, inefficient, and difficult to integrate with standard CMOS processing, and they struggle to withstand voltages above 5V without increasing size or using expensive materials like SiC or GaN.
Innovation Solution
The development of high-voltage transistors using a standard low-voltage process that incorporates dummy polysilicon structures and interstitial implant resistance pockets within the drift region, allowing for independent biasing to modulate conductivity and protect against high voltages, while maintaining a compact size and low cost.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional high-voltage transistor structures are used, then breakdown voltage can be increased, but device area increases significantly
Solution Approach 1:
The drift region is segmented into multiple sections with different doping concentrations (first drift region with lower doping, second drift region with higher doping). This segmentation allows the transistor to achieve high breakdown voltage through the first drift region while the second drift region provides compactness, thus resolving the contradiction between breakdown voltage and device area.
Solution Approach 2:
Different regions of the drift structure are assigned different doping qualities - the first drift region has lower doping concentration for high voltage handling, while the second drift region has higher doping concentration for compact design. This local quality differentiation enables the device to achieve both high breakdown voltage and small area.
2Reliability
If specialized processing and exotic materials are used for high-voltage transistors, then voltage handling capability improves, but manufacturing cost increases
Solution Approach 1:
The transistor structure uses standard silicon-based CMOS processing techniques that can serve both low-voltage and high-voltage applications. The same fabrication process creates both the first and second drift regions with different doping, eliminating the need for specialized high-voltage processing and exotic materials, thus reducing manufacturing cost while maintaining voltage handling capability.
Solution Approach 2:
The invention achieves high voltage handling by changing doping parameters (concentration and distribution) within standard silicon material, rather than requiring exotic materials. The dual-drift region structure with varying doping concentrations allows standard CMOS processes to produce high-voltage transistors, reducing manufacturing complexity and cost.
3Ease of manufacture
If standard CMOS processing is used, then manufacturing cost decreases, but voltage handling capability is limited to below 5V
Solution Approach 1:
The drift region is divided into two segmented sections with different doping concentrations, allowing standard CMOS processing to achieve high voltage handling. The first drift region handles the high voltage stress while the second drift region enables compact design, breaking through the 5V limitation of conventional single-region structures.
Solution Approach 2:
The invention creates a composite doping structure within the drift region, combining two regions with different doping concentrations in a single silicon-based device. This composite structure enables standard CMOS processing to produce transistors with voltage handling capability exceeding 5V, overcoming the limitation of conventional single-doping structures.
4Area of stationary object
If device size is reduced for compactness, then integration density improves, but breakdown voltage decreases
Solution Approach 1:
The second drift region with higher doping concentration is positioned adjacent to the gate structure where compactness is critical, while the first drift region with lower doping extends further to provide high breakdown voltage. This local quality assignment allows the device to be compact overall while maintaining high voltage handling capability.
Solution Approach 2:
Segmenting the drift region into two functional sections allows the device to achieve compact size through the second drift region while the first drift region provides the necessary breakdown voltage. The segmentation enables independent optimization of each region for its specific function, resolving the contradiction between size and breakdown voltage.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables transistors to handle voltages exceeding 5V with reduced size and cost, integrating well with standard CMOS processing, and providing enhanced breakdown voltage and reduced hot carrier injection, thus addressing the limitations of existing high-voltage transistor technologies.
Implementation Method 1
interstitial implant resistance pockets (IRP's) formed within the drift region between the gate structure and an adjacent DPS
Implementation Method 2
the breakdown voltage, BVDSS (sometimes called VBDSS) of a MOSFET is the drain-source voltage at which no more than a specified drain current may flow at a specified temperature and with zero gate-source voltage [noting that breakdown of a MOSFET may be caused by various effects, being primarily avalanche breakdown (i.e., drain-channel driven breakdown)]
Data Source
AI summary
High-voltage transistors that may be fabricated in a standard low-voltage process. Embodiments include integrated circuits that combine, in a unitary structure, an LDMOS FET device that includes one or more dummy polysilicon structures (DPS's) overlying a drift region and comparable in configuration to the FET gate, and interstitial implant resistance pockets (IRP) formed within the drift region between the gate and an adjacent DPS and between each pair of adjacent DPS's. The IRPs may be augmented with floating contacts to remove heat from the drift region and provide additional shielding of the drain contact from the nearest edge of the gate. The IRPs may be biased to modulate the conductivity of the drift region. The DPS's may be biased to modulate the conductivity of the drift region, and in such a way as to protect each DPS from excessive and potentially destructive voltages.