LDMOS Gate Structure with Drift Gate for Interface Defects

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Solution Overview

Problem

Existing LDMOS devices face performance and reliability issues due to interface defects caused by high temperature annealing during the fabrication process, leading to hot carrier effects and reduced current flow, which can result in device shutdown.

Innovation Solution

A second gate structure is introduced in the drift region, configured between the first gate structure and the drain, with a second isolation layer that reduces charge accumulation at the interface between the second gate and the substrate, improving device performance and reliability by applying a reverse voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If high temperature annealing is performed during fabrication, then device performance is improved, but interface defects are generated causing hot carrier effects and reduced reliability

Engineering Contradiction:
Improvedevice reliabilityVSAvoidinterface defects
Core Design Contradiction:
ReliabilityVSObject-affected harmful factors

Solution Approach 1:

A second gate structure is introduced as an intermediary element between the first gate structure and the drain region. This second gate structure includes a second isolation layer that acts as a mediator to reduce charge accumulation at the interface between the drift region and the substrate, thereby mitigating hot carrier effects and interface defects while maintaining device performance

Inventive Principle:
Principle #24Intermediary (Mediator)

Solution Approach 2:

The gate structure is segmented into a first gate structure and a second gate structure. The first gate structure controls the channel, while the second gate structure specifically addresses interface defects in the drift region. This segmentation allows independent optimization of channel control and interface quality without compromising overall device reliability

Inventive Principle:
Principle #1Segmentation

2Object-affected harmful factors

If a second gate structure is added to reduce charge accumulation, then interface defect impact is mitigated, but device complexity increases

Engineering Contradiction:
Improvecharge accumulationVSAvoidgate structure complexity
Core Design Contradiction:
Object-affected harmful factorsVSDevice complexity

Solution Approach 1:

The second gate structure is merged with the first gate structure sharing common components including the gate dielectric layer, gate electrode, and surrounding dielectric structures. This merging approach reduces fabrication complexity and material usage while still providing the beneficial effect of reduced charge accumulation at the interface

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS20230402540A1Semiconductor structure and fabrication method thereof
Publication Date: 2023.12.14 SEMICON MFG INT (SHANGHAI) CORP
  • US20230402540A1 patent drawing
  • US20230402540A1 patent drawing
  • US20230402540A1 patent drawing

AI summary

A semiconductor structure includes a substrate, a body region and a drift region in the substrate, a first gate structure over the body region and the drift region, a second gate structure over the drift region, a source in the body region, and a drain in the drift region. The first gate structure is between the source and the drain. The second gate structure is between the first gate structure and the drain.