RF LDMOS Drift Region Junction Depth Optimization
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Solution Overview
Problem
Conventional RF LDMOS devices have a shallow drift region junction depth that restricts their cutoff frequencies due to high resistance, limiting their operational performance in high-frequency applications.
Innovation Solution
The RF LDMOS device is fabricated with a drift region junction depth comparable to that of the channel well regions, achieved through a multi-step implantation process that adjusts doping concentrations and energies, resulting in a significant reduction of resistance and enhancement of cutoff frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the drift region has a shallow junction depth to maintain high resistance for breakdown voltage improvement, then breakdown voltage is improved, but cutoff frequency is restricted due to high resistance
Solution Approach 1:
The drift region is segmented into multiple doping zones with different doping concentrations. The upper portion has lighter doping to maintain high resistance and breakdown voltage, while the lower portion has heavier doping to reduce resistance and enhance cutoff frequency. This segmentation allows simultaneous optimization of both breakdown voltage and cutoff frequency.
Solution Approach 2:
Different regions of the drift region are assigned different doping concentrations to achieve different local properties. The upper drift region maintains light doping for high resistance characteristics needed for breakdown voltage, while the lower drift region has heavy doping for low resistance characteristics needed for cutoff frequency enhancement.
2Strength
If the drift region has a shallow junction depth to maintain high resistance, then breakdown voltage is improved, but resistance remains high limiting operational performance
Solution Approach 1:
The drift region is divided into upper and lower portions with different doping concentrations. The upper portion maintains light doping for high resistance and breakdown voltage, while the lower portion has heavy doping to reduce overall resistance and minimize energy loss in the drift region.
Solution Approach 2:
The drift region incorporates local quality variations through selective doping concentrations at different depths. The upper region maintains high resistance for breakdown voltage while the lower region has reduced resistance to minimize energy loss, achieving both objectives simultaneously.
3Reliability
If a multi-step implantation process is used to adjust doping concentrations and energies to increase junction depth, then cutoff frequency is enhanced, but device complexity increases
Solution Approach 1:
The doping process is segmented into multiple implantation steps, each targeting specific depth regions with appropriate doping concentrations and energies. This segmented approach enables precise control of the drift region's doping profile to achieve the desired junction depth and cutoff frequency enhancement.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design increases the cutoff frequencies of RF LDMOS devices by approximately 10GHz, improving their performance in high-frequency applications by matching the junction depth of the drift region with the channel well regions.
Implementation Method 1
achieved through a multi-step implantation process that adjusts doping concentrations and energies
Data Source
Figure 1
Figure 2
Figure 3A~3B
AI summary
A semiconductor device includes a well region of a first conductivity type, having a first depth, formed in a substrate. A source contact region of a second conductivity type is formed in the well region. A drift region of the second conductivity type, having a second depth greater than 50% of the first depth, is formed in the substrate adjacent to the well region. A drain contact region of the second conductivity type is formed in the drift region. A gate electrode is formed on the substrate between the source contact region and the drain contact region. The drain contact region is spaced apart from the gate electrode and the source contact region is adjacent to the gate electrode. Furthermore, a method of fabricating a semiconductor device is also provided. The method includes performing a multi-step implantation process to form a drift region.