LDMOS Drift Region Layout for Breakdown Voltage and Avalanche Control
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Solution Overview
Problem
LDMOS transistors face a trade-off between high breakdown-voltage and low ON-resistance, with avalanche breakdown reducing breakdown voltage, and existing structures exacerbate electric field concentration.
Innovation Solution
A semiconductor device with a P-type diffusion region extended below an N-type drift region, featuring a buried oxide layer and strategically set distances to alleviate electric field intensity, ensuring an electric field intensity of 0.35 MV/cm or less in critical regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the P-type diffusion region is extended and disposed below an N-type drift region, then the electric field concentration between gate and drain is alleviated, but the intensity of electric field between P-type diffusion region and N-type drain region increases causing avalanche breakdown
Solution Approach 1:
The patent applies local quality by creating a P-type semiconductor region with specific local properties (conductivity type and positioning) beneath the drift region. This localized structural modification alters the electric field distribution specifically in the critical region between the P-type diffusion region and N-type drain region, preventing avalanche breakdown while maintaining overall device performance.
Solution Approach 2:
The P-type semiconductor region acts as an intermediary structure between the P-type diffusion region and the N-type drain region. By introducing this intermediate layer, the patent modifies the electric field distribution and prevents direct high-field interaction between the diffusion region and drain region, thereby avoiding avalanche breakdown.
2Reliability
If the breakdown voltage is increased, then the transistor can handle higher voltages when OFF, but the ON-resistance increases reducing efficiency
Solution Approach 1:
The patent employs parameter changes by carefully controlling the conductivity type, positioning, and dimensional parameters of the P-type semiconductor region. By optimizing these parameters, the invention achieves a balance between breakdown-voltage and ON-resistance, allowing the transistor to handle high voltages when OFF while maintaining low resistance when ON through precise structural configuration.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration increases breakdown-voltage while avoiding reductions due to avalanche breakdown, achieving a desired breakdown voltage of 60 V or more by optimizing electric field distribution.
Implementation Method 1
a buried oxide layer provided at least under an end portion, of the gate electrode, toward the drain region, the buried oxide layer being formed to be buried from a top face of the semiconductor substrate, and the buried oxide layer being configured to alleviate an electric field
Implementation Method 2
the first distance and the second distance are set so that an intensity of 0.35 MV/cm or less is observed in an electric field of a first region including the end portion of the drift region and in an electric field of a second region between the end of the semiconductor region and the drain region
Data Source
AI summary
A semiconductor device includes a semiconductor substrate of a first conductivity type, a body region of the first conductivity type, a source region of a second conductivity type, a drain region of the second conductivity type, a gate electrode, a drift region of the second conductivity type, an implanted oxide layer, and a semiconductor region of the first conductivity type. The semiconductor region is formed to extend in a direction along the top face of the semiconductor substrate. A first distance and a second distance are set so that an intensity of 0.35 MV/cm or less is observed in an electric field of a first region including the end portion of the drift region and in an electric field of a second region between the end of the semiconductor region and the drain region.