LDMOS Drift Region Stressor Layers for Mobility and Breakdown Voltage

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Solution Overview

Problem

As semiconductor circuits, such as LDMOS devices, continue to downscale for high voltage applications, there is a challenge in maintaining voltage performance due to decreasing carrier mobility in the drift region, requiring a new semiconductor device design to improve carrier mobility while maintaining breakdown voltage.

Innovation Solution

The semiconductor device incorporates a pair of stressor layers that impose reverse stresses to the drift region, enhancing the mobility of both PMOS and NMOS devices, and includes a stressor structure to control carrier mobility, along with a silicide layer and silicide blocking layer to manage the electric field and doping concentration.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If semiconductor circuits continue to downscale for high voltage applications, then device size is reduced, but carrier mobility and voltage performance deteriorate

Engineering Contradiction:
Improvedevice sizeVSAvoidcarrier mobility and voltage performance
Core Design Contradiction:
Volume of moving objectVSReliability

Solution Approach 1:

The patent applies different stress conditions to different regions of the drift region by forming first and second stressor layers with opposite stress directions. The first stressor layer applies compressive stress while the second stressor layer applies tensile stress, creating locally optimized carrier mobility in different areas of the device while maintaining overall device miniaturization.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The patent changes the physical state of the drift region by introducing stressor layers that modify the crystal lattice structure through mechanical stress. This alters the carrier mobility parameter without changing the device dimensions, allowing performance improvement in scaled-down devices.

Inventive Principle:
Principle #35Parameter changes

2Reliability

If stressor layers are added to enhance carrier mobility, then electrical properties improve, but device complexity increases

Engineering Contradiction:
Improveelectrical properties and carrier mobilityVSAvoidstructure complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent combines multiple functions into the stressor layer structure: the first and second stressor layers not only provide opposite stresses to enhance carrier mobility but also serve as part of the device's structural framework. This integration reduces the need for separate components and minimizes overall device complexity.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The stressor layers serve multiple purposes: they enhance carrier mobility through mechanical stress, maintain device structural integrity, and enable the device to handle high voltage applications. This multi-functionality reduces the need for additional components and simplifies the overall device architecture.

Inventive Principle:
Principle #6Universality (Multi-functionality)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach improves the electrical properties of the semiconductor device while maintaining the breakdown voltage, effectively addressing the mobility and voltage performance issues in downscaled LDMOS devices.

Implementation Method 1

The first stressor layer is configured to apply a first stress to the drift region of the substrate

Methodology Applied
Scientific EffectStress:

Implementation Method 2

The second stressor layer is configured to apply a second stress to the drift region of the substrate

Methodology Applied
Scientific EffectStress:

Data Source

PatentUS20240079493A1Semiconductor device and method of manufacturing the same
Publication Date: 2024.03.07 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240079493A1 patent drawing
  • US20240079493A1 patent drawing
  • US20240079493A1 patent drawing

AI summary

A semiconductor device and method of manufacturing the same are provided. The semiconductor device includes a substrate and a gate structure disposed on the substrate. The semiconductor device also includes a source region and a drain region disposed within the substrate. The substrate includes a drift region laterally extending between the source region and the drain region. The semiconductor device further includes a first stressor layer disposed over the drift region of the substrate. The first stressor layer is configured to apply a first stress to the drift region of the substrate. In addition, the semiconductor device includes a second stressor layer disposed on the first stressor layer. The second stressor layer is configured to apply a second stress to the drift region of the substrate, and the first stress is opposite to the second stress.