LDMOS Device Dual Field Plate Electric Field Control
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Solution Overview
Problem
LDMOS devices face challenges in achieving high breakdown voltage and low On resistance, as increasing the width of the field oxide to enhance breakdown voltage leads to increased electric field at the gate electrode edge, potentially causing surface breakdown and higher On resistance, especially when operating at high voltages.
Innovation Solution
The introduction of a second field plate with a different bias applied to it, isolated from the first field plate, allows for a higher breakdown voltage and lower On resistance without extending the width of the gate insulating layer, and the use of a buried layer and multiple wells with specific doping and insulating layers to control the electric field effectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Strength
If the width of the field oxide is increased to enhance breakdown voltage, then the breakdown voltage is improved, but the electric field at the gate electrode edge increases causing surface breakdown and higher On resistance
Solution Approach 1:
The single field plate structure is segmented into multiple field plates (first field plate and second field plate) spaced apart from each other. This segmentation distributes the electric field control function across multiple elements, allowing the device to achieve high breakdown voltage without concentrating excessive electric field at any single location, thereby preventing surface breakdown while maintaining low On resistance.
Solution Approach 2:
Additional field plates are introduced as intermediary elements between the gate electrode and the drain region. These intermediary field plates modify the electric field distribution in the drift region, creating a more gradual field gradient that prevents field concentration at the gate edge while still providing the necessary voltage blocking capability.
2Strength
If the width of the field oxide is increased to enhance breakdown voltage, then the breakdown voltage is improved, but the On resistance increases
Solution Approach 1:
The field plate structure is divided into multiple segments (first and second field plates) with spacing between them. This segmentation allows the electric field to be distributed more evenly across the drift region, reducing field concentration effects that would otherwise require a wider field oxide. The spaced configuration maintains effective voltage blocking while preserving lower On resistance by avoiding excessive field-induced carrier depletion.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables the LDMOS device to operate with a higher breakdown voltage and lower On resistance, reducing the likelihood of surface breakdown while maintaining low resistance, thus improving its performance for high-voltage applications.
Implementation Method 1
The field insulator is formed on a surface of the first well... a first field plate formed on a predetermined portion of the field insulator... and a second field plate formed on another predetermined portion of the field insulator
Implementation Method 2
a buried layer formed in a first conductive type substrate and doped with a second conductive type impurity; a first well formed in the buried layer and doped with the first conductive type impurity... a second well formed in the first well at one side of the field insulator and doped with the first conductive type impurity
Data Source
AI summary
Provided is a LDMOS device and method for manufacturing. The LDMOS device includes a second conductive type buried layer formed in a first conductive type substrate. A first conductive type first well is formed in the buried layer and a field insulator with a gate insulating layer at both sides are formed on the first well. On one side of the field insulator is formed a first conductive type second well and a source region formed therein. On the other side of the field insulator is formed an isolated drain region. A gate electrode is formed on the gate insulating layer on the source region and a first field plate is formed on a portion of the field insulator and connected with the gate electrode. A second field plate is formed on another portion of the field insulator and spaced apart from the first field plate.