Dual-Section LDMOS Gate Structure for BVdss and Gm Tradeoffs
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Solution Overview
Problem
LDMOSFETs experience performance degradation with device size scaling and operation at higher voltages, leading to reduced drain-to-source breakdown voltage (BVdss) and transconductance (Gm), which complicates modern IC design aiming for performance improvement, size scaling, and power consumption optimization.
Innovation Solution
The semiconductor device incorporates a gate with two sections, where the first gate section has a thick gate dielectric layer and an optional additional gate conductor layer, and the second gate section has a thinner gate dielectric layer, with a gate sidewall spacer positioned laterally adjacent to the second gate section, enhancing BVdss and Gm for improved operation at higher voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size scaling is performed to improve integration, then productivity increases, but performance degrades including reduced BVdss and Gm
Solution Approach 1:
The gate structure is divided into two distinct sections with different gate dielectric thicknesses. The first gate section has a thicker gate dielectric layer to maintain high breakdown voltage and transconductance for power handling, while the second gate section has a thinner gate dielectric layer optimized for switching performance. This local differentiation allows each section to be optimized for its specific function, resolving the contradiction between size scaling and performance maintenance.
Solution Approach 2:
The gate is segmented into two functional sections: a first gate section for power amplification with thick gate dielectric, and a second gate section for switching with thin gate dielectric. This segmentation enables independent optimization of each section's characteristics, allowing the device to maintain high BVdss and Gm while achieving better integration density through compact layout.
2Power
If operation voltage is increased to improve power output, then power increases, but performance degradation occurs including reduced BVdss
Solution Approach 1:
The first gate section with thicker gate dielectric is specifically designed to handle high voltage operations with improved breakdown characteristics, while the second gate section with thinner gate dielectric handles switching operations. This local quality differentiation allows the device to operate at higher voltages for increased power output without suffering from uniform gate structure limitations that cause BVdss degradation.
3Speed
If gate dielectric thickness is reduced to improve switching speed, then speed increases, but breakdown voltage decreases
Solution Approach 1:
The gate is divided into two sections where the second gate section has thinner gate dielectric optimized for fast switching operations, while the first gate section maintains thicker gate dielectric for high breakdown voltage. This segmentation allows the device to achieve improved switching speed through the thin-dielectric section without compromising overall breakdown voltage performance, as the thick-dielectric section continues to provide voltage blocking capability.
Data Source
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AI summary
Disclosed are embodiments of a semiconductor device and method of forming the device. The device includes a gate with first and second sections on a semiconductor layer. The first section includes first gate dielectric and gate conductor layers and an optional additional gate conductor layer on the first gate conductor layer. The second section includes second gate dielectric and gate conductor layers on the semiconductor layer and further extending onto the top of the first gate conductor layer. The second gate dielectric layer is thinner than the first gate dielectric layer. A gate sidewall spacer is on the first gate conductor layer positioned laterally to a sidewall of the second section (e.g., between the sidewall and the optional additional gate conductor layer). The first and second sections are either electrically connected for biasing with the gate bias voltage or electrically isolated for biasing with different gate bias voltages.