LDMOS Structure with Dual Ground Plane for Breakdown Voltage
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Solution Overview
Problem
Lateral double-diffused MOSFET (LDMOS) devices face challenges with reduced breakdown voltage and increased self-heating due to thermal isolation, which affects their performance in advanced semiconductor devices, particularly at 22 FDSOI technology nodes, where reducing on-resistance while maintaining or increasing breakdown voltage is essential for energy efficiency and wireless connectivity applications.
Innovation Solution
A semiconductor device structure with a semiconductor-on-insulator (SOI) configuration, featuring a dual ground plane region with counter-doped well regions and a deep well region, along with a gate structure, source, and drain regions, forms a channel drift junction that is overlain by the gate, reducing on-resistance and maintaining or enhancing breakdown voltage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If LDMOSFET devices are used with conventional structures, then manufacturing compatibility with VLSI technologies is improved, but breakdown voltage is reduced due to vertical and horizontal breakdown possibilities
Solution Approach 1:
The patent transitions from conventional planar LDMOSFET structures to a three-dimensional suspended structure where the active region is elevated above the substrate using sacrificial oxides. This dimensional change creates additional space for optimized doping profiles and junction depths, enabling higher breakdown voltage while maintaining manufacturing compatibility through standard CMOS-compatible processes.
Solution Approach 2:
The patent implements non-uniform doping concentrations within the active region, with heavily doped source/drain regions and lightly doped drift regions. The counter-doped well regions create localized electric field modulation that enhances breakdown voltage specifically in critical areas without affecting overall device manufacturability.
2Adaptability or versatility
If LDMOSFET devices are used with conventional structures, then integration with logic device construction elements is improved, but on-resistance is increased which affects energy efficiency
Solution Approach 1:
By suspending the active region above the substrate, the patent creates vertical space that allows for optimized source-drain spacing and channel length control. This three-dimensional configuration enables lower on-resistance through improved carrier transport paths while maintaining compatibility with standard logic device integration techniques.
Solution Approach 2:
The patent optimizes critical parameters including channel length, drift region length, and doping concentrations to minimize on-resistance. The suspended structure allows independent control of these parameters without being constrained by substrate interactions, enabling parameter optimization for energy efficiency while preserving integration capabilities.
3Device complexity
If LDMOSFET devices are used with conventional structures, then device complexity is reduced, but self-heating is increased due to thermal isolation of SiO2
Solution Approach 1:
The patent divides the device structure into distinct functional regions: the suspended active region, the substrate, and the sacrificial oxide layer. This segmentation allows thermal management optimization by creating controlled thermal pathways through the sacrificial oxides while maintaining the overall structural simplicity needed for manufacturing.
Solution Approach 2:
The sacrificial oxides serve as thermal intermediaries between the suspended active region and the substrate. These oxides provide controlled thermal isolation that reduces self-heating in the active region while still allowing heat dissipation pathways, thus managing temperature without significantly increasing device complexity.
4Productivity
If advanced technology nodes (22 nm FDSOI) are targeted, then integration density is improved, but maintaining breakdown voltage while reducing on-resistance becomes more difficult
Solution Approach 1:
At advanced 22 nm FDSOI nodes, the patent utilizes the vertical dimension created by the suspended structure to accommodate optimized doping profiles and junction depths that would be impossible in planar configurations. This enables maintaining high breakdown voltage despite the scaled dimensions required for high integration density.
Solution Approach 2:
The patent implements localized doping optimization in critical regions such as the drift region and channel-drift junction, with counter-doped well regions providing localized electric field control. This allows breakdown voltage maintenance in scaled devices while preserving the high integration density required for advanced technology nodes.
Data Source
AI summary
The present disclosure provides a semiconductor device structure including an active region having a semiconductor-on-insulator (SOI) configuration, a semiconductor device of lateral double-diffused MOS (LDMOS) type, a dual ground plane region formed by two well regions which are counter-doped to each other, the dual ground plane region extending below the semiconductor device, and a deep well region extending below the dual ground plane region. Herein, the semiconductor device of LDMOS type comprises a gate structure formed on the active region, a source region and a drain region formed in the active region at opposing sides of the gate structure, and a channel region and a drift region, both of which being formed in the active region and defining a channel drift junction, wherein the channel drift junction is overlain by the gate structure.